System and method for conditionally executing an instruction dependent on a previously existing condition

A system, comprising:

• a memory system and a processor coupled to the memory system;
• wherein the memory system comprises a conditional execution instruction and at least one target instruction, and wherein the conditional execution instruction specifies the at least one target instruction, a register, and a condition within the register;
• wherein the processor comprises:
• a first flag register and a second flag register;
• an instruction unit configured to process the conditional execution instruction and the least one target instruction from the memory system;
• an execution unit operably coupled to the instruction unit and configured to save a result of the at least one target instruction dependent upon the existence of the specified condition in the specified register during execution of the conditional execution instruction;
• and
• wherein in the event the conditional execution instruction specifies the first flag register, the execution unit is configured to copy the value of the flag bit to a corresponding flag bit of the second flag register, and to save a result of the at least one target instruction dependent upon the specified condition in the first flag register during execution of the conditional execution instruction.

A method for conditionally executing at least one instruction, the method comprising:

• inputting a conditional execution instruction and an at least one target instruction, wherein the conditional execution instruction specifies the at least one target instruction, a register, and a condition within the register;
• performing the following in the event the conditional execution instruction specifies a first flag register:
• copying a value of a plurality of flag bits in the first flag register to a corresponding plurality of flag bits in a second flag register;
• and
• saving a result of the at least one target instruction dependent upon the specified condition in the first flag register during execution of the conditional execution instruction.

A processor, comprising:

• means for inputting a conditional execution instruction and at least one target instruction, wherein the conditional execution instruction specifies the at least one target instruction, a register, and a condition within the register;
• means for performing the following in the event the conditional execution instruction specifies a first flag register:
• copying the value of a flag bit of the first flag register to a corresponding flag bit of a second flag register;
• and
• saving a result of the at least one target instruction dependent upon the specified condition in the first flag register during execution of the conditional execution instruction.