Hierarchical scheduling windows
OwnerBryan P. Black, Edward A. Brekelbaum +1inventors
InventorsBryan P. Black, Edward A. Brekelbaum, Jeff P. Rupley II
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Abstract
A scheduling window hierarchy to facilitate high instruction level parallelism by issuing latency-critical instructions to a fast schedule window or windows where they are stored for scheduling by a fast scheduler or schedulers and execution by a fast execution unit or execution cluster. Furthermore, embodiments of the invention pertain to issuing latency-tolerant instructions to a separate scheduler or schedulers and execution unit or execution cluster.
Claims30
An apparatus comprising:
- a first schedule window;
- a second schedule window coupled to the first schedule window, the first schedule window being larger than the second schedule window;
- a first unit to schedule a first instruction stored in the first schedule window without the first instruction being stored in the second schedule window before being scheduled.
A system comprising:
- a memory unit, the memory unit comprising a latency-tolerant instruction and a latency-intolerant instruction;
- a processor to fetch the latency-tolerant instruction from the memory unit before fetching the latency-intolerant instruction and to output a result of executing the latency-intolerant instruction before a result of executing the latency-tolerant instruction.
A method comprising:
- fetching a first instruction and a second instruction from a memory;
- determining the scheduling latency-tolerance of the first and second instructions;
- executing the first instruction before the second instruction if the first instruction is less tolerant of scheduling latency than the second instruction;
- executing the second instruction before the first instruction if it is less tolerant of scheduling latency than the first instruction.
A machine-readable medium having stored thereon a set of instructions, which when executed by a machine cause the machine to perform a method comprising:
- fetching a plurality of instructions;
- organizing the plurality of instructions according to scheduling latency tolerance of each of the plurality of instructions, the organizing comprising storing latency-tolerant instructions in a first scheduling window and storing latency-intolerant instructions in at least a second scheduling window, the first scheduling window being larger than the at least second scheduling window;
- scheduling the plurality of instructions for execution according to scheduling latency tolerance of the plurality of instructions, the latency-tolerant instructions being scheduled at a slower rate than the latency-intolerant instructions;
- executing the plurality of instructions according to schedule latency tolerance of the plurality of instructions, the latency-tolerant instructions being executed at a slower rate than the latency-intolerant instructions.
An apparatus comprising:
- first means for grouping a plurality of latency-tolerant instructions together;
- second means for grouping a plurality of latency-intolerant instructions together, the latency-intolerant instructions being fewer in number than the latency-tolerant instructions;
- first means for scheduling the plurality of latency-tolerant instructions without the plurality of latency-tolerant instructions being first grouped by said second means for grouping;
- second means for scheduling the plurality of latency-intolerant instructions, the first means for scheduling the plurality of latency-tolerant instructions being a slower means than the second means for scheduling the plurality of latency-tolerant instructions;
- first means for providing source data to the latency-tolerant instructions;
- second means for providing source data to the latency-intolerant instructions;
- first means for executing the latency-tolerant instructions;
- second means for executing the latency-intolerant instructions, the second means for executing the latency-intolerant instructions being a faster means than the first means for executing the latency-tolerant instructions.
Dependencies are inferred from the claim text.