64-Bit single cycle fetch scheme for megastar architecture
AssigneeTexas Instruments Incorporated
InventorsRoshan J. Samuel, Jason D. Kridner
Life of this patent
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Abstract
The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates 32-bit memory blocks arranged into separate entities or banks. Because the parent CPU has only three 16-bit buses, a maximum read in one clock cycle through the memory interface would normally be 48-bits. This invention describes an approach for a fetch method involving tapping into the memory bank data at an earlier stage prior to the memory interface. This allows the normal 48-bit fetch to be extended to 64-bits as required for full performance of the numerical processor accelerator and other speed critical operations and functions.
Claims8
A data processing apparatus comprising:
- a central processor unit having three N-bit composite busses each of said busses carrying data, address, and control words;
- an internal memory partitioned into two memory banks;
- a memory interface unit connecting said central processor unit and said internal memory, said memory interface unit responsive to two addresses for supplying said central processor unit an N-bit data words from each memory bank corresponding to a first address on a first N-bit composite bus and one N-bit data from a selected memory bank corresponding to a second address on a second N-bit composite bus;
- and
- a numerical co-processor receiving three N-bit data words from said central processor unit and one N-bit data word from a memory bank opposite to said selected memory bank corresponding to said second address.
Dependencies are inferred from the claim text.