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AssigneeSun Microsystems, Inc.
InventorsSudheendra Hangal, Durgam Vahia, Juin-Yeu Lu
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A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.
A system for verifying a memory consistency model on a shared memory multiprocessor computer system, the memory consistency model specifying the semantics of memory operations for the plural processors of the multiprocessor computer system, the system comprising:
A method for verifying the memory consistency model on a shared memory multiprocessor computer system, the method comprising:
A method for testing a memory subsystem of a computer having plural processors that share access to the memory subsystem under a memory consistency model, the method comprising:
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