System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system

A multiprocessor computer system, comprising:

• a plurality of nodes, each node including:
• an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory;
• a memory cache for caching a multiplicity of memory lines of information, including memory lines of information stored in a remote memory subsystem that is local to another node;
• the directory including an entry associated with a memory line of information stored in the local memory subsystem, the entry including an identification field for identifying a subset of nodes from the plurality of nodes caching the memory line of information;
• the identification field configured to comprise a plurality of bits at associated positions within the identification field;
• a protocol engine implementing a cache coherence protocol, said protocol engine configured to
• associate with each respective bit of the identification field one or more nodes of the plurality of nodes, including a respective first node, wherein the one or more nodes associated with each respective bit are determined by reference to the position of the respective bit within the identification field;
• set each bit in the identification field of the directory entry associated with the memory line for which the memory line is cached in at least one of the associated nodes;
• send an initial invalidation request to no more than a first predefined number of the nodes associated with set bits in the identification field of the directory entry associated with the memory line.