Method and apparatus for optimizing line writes in cache coherent systems

A method comprising:

• allocating a cache line;
• loading data to fill the cache line responsive to an indication that a plurality of buffered stores does not fill the cache line;
• and
• not loading data to fill the cache line responsive an indication that the plurality of buffered stores does fill the cache line.

An apparatus comprising:

• a store buffer to hold a coalesced plurality of stores;
• a flag associated with the store buffer to indicate whether the coalesced plurality of stores fills a cache line;
• and
• control logic coupled with the store buffer to allocate the cache line, the control logic loading data to fill the cache line responsive to said flag indicating that the coalesced plurality of stores does not fill the cache line, and the control logic not loading data to fill the cache line responsive to the flag indicating that the coalesced plurality of stores does fill the cache line.

A data processing system comprising:

• an addressable memory to store display frame data;
• a first agent including:
• a first buffer to hold a plurality of stores;
• and
• a first cache control logic coupled with the first buffer to allocate a cache line, the first cache control logic signaling to load data to fill the cache line responsive to one or more buffered stores of the plurality of stores not filling the cache line, and the first cache control logic signaling not to load data to fill the cache line responsive to a coalesced set of stores of the plurality of stores filling the cache line;
• and
• memory control logic coupled with the addressable memory and responsive to the cache control logic signaling to load data, to transfer display frame data to fill the cache line, and responsive to the cache control logic signaling not to load data, not to transfer display frame data to fill the cache line.