Claiming cycles on a processor bus in a system having a PCI to PCI bridge north of a memory controller
AssigneeIntel Corporation
InventorVarghese George
Life of this patent
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Abstract
In one embodiment, the invention provides a method comprising determining information about an input/output device located north of the memory controller; and controlling a response of the memory controller to read/write requests on a processor bus to a bus agent on a system bus south of the memory controller based on the information.
Claims28
A method comprising:
- determining information about an input/output device located north of a memory controller;
- and
- controlling a response of the memory controller to read/write requests on a processor bus to a bus agent on a system bus south of the memory controller based on the information.
A method comprising:
- replicating configuration information for a logical bus located north of a memory controller in a memory controller;
- and
- controlling a response of the memory controller to a central processing unit initiated bus transaction intended for a responding agent on a system bus located south of the memory controller based on the replicated configuration information.
A system comprising:
- a central processing unit;
- a memory controller;
- a system bus south of the memory controller and coupled thereto;
- at least one first input/output device coupled to the system bus;
- a processor bus north of the memory controller bridging the central processing unit and the memory controller;
- and
- at least one second input/output device integrated with the central processing unit;
- wherein the memory controller stores configuration information for the or each second input/output device, and controls its response to input/output read/write request based on the configuration information.
The system of claim 21, wherein the configuration information comprises information in the following registers of the software defined PCI-to-PCI bridge:
- command register, secondary, bus #, subordinate bus #, I/O base, I/O limit, memory base, memory limit, prefetchable memory base, prefetchable memory limit, prefetchable base upper 32 bits, prefetchable limit upper 32 bits, and bridge control register.
A system comprising:
- a central processing unit, including at least one input/output device on a logical PCI bus and a software defined PCI-to-PCI bridge storing configuration information for the or each input/output device;
- a memory controller which stores configuration information from the software defined PCI-to-PCI bridge;
- and
- a PCI system bus south of the memory controller and coupled thereto;
- a processor bus bridging communications between the CPU and the memory controller, wherein the memory controller uses the configuration information to determine when to claim read/write cycles on the processor bus.
The system of claim 25, wherein the or each input/output device is a digital signal processor configured to process communications data.
Dependencies are inferred from the claim text.