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US 2004/0063295 A1Published application
One-mask process flow for simultaneously constructing a capacitor and a thin film resistor
AssigneeIntel Corporation
InventorsStephen T. Chambers, Rick Davis, Philip Yashar
Life of this patent
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Abstract
A method includes forming a first damascene interconnect layer in a first dielectric. A first dielectric film is deposited on the first dielectric and on the first damascene interconnect layer. A conductor layer is deposited on the first dielectric film. The conductor layer is patterned, via a single mask, to form a first conductor and a second conductor. The first damascene interconnect level, the first dielectric film, and the first conductor form a capacitor and the second conductor forms a resistor.
Claims28
A method, comprising:
- forming a first damascene interconnect level in a first dielectric layer;
- depositing a first dielectric film on the first dielectric and on the first damascene interconnect layer;
- depositing a conductor layer on the first dielectric film;
- and
- patterning the conductor layer, via a single mask, to form a first conductor and a second conductor,
- wherein the first damascene interconnect level, the first dielectric film, and the first conductor form a capacitor and the second conductor forms a resistor.
3 more elements
A method, comprising:
- depositing a first dielectric film on a first dielectric and on a first damascene interconnect level;
- depositing a conductor layer on the first dielectric film;
- patterning the conductor layer, via a single mask, to form a first conductor and a second conductor,
- wherein the first damascene interconnect level, the first dielectric film, and the first conductor form a capacitor and the second conductor forms a resistor;
- and
- depositing a second damascene interconnect level on the conductor layer after the patterning.
3 more elements
An article comprising:
- a storage medium having stored thereon first instructions that when executed by a machine result in the following:
- forming a first damascene interconnect level in a first dielectric layer;
- depositing a first dielectric film on the first dielectric and on the first damascene interconnect layer;
- depositing a conductor layer on the first dielectric film;
- and
- patterning the conductor layer, via a single mask, to form a first conductor and a second conductor,
- wherein the first damascene interconnect level, the first dielectric film, and the first conductor form a capacitor and the second conductor forms a resistor.
4 more elements
Dependencies are inferred from the claim text.