Nanometer-scale semiconductor devices and method of making

A semiconductor device, comprising:

• a substrate;
• a base epitaxial semiconducting layer including a dopant of a first polarity disposed over said substrate;
• a first semiconducting layer including a dopant of a second polarity disposed over said substrate;
• and
• a first junction formed between said base epitaxial semiconducting layer and said first semiconducting layer, said first junction having an area having at least one lateral dimension less than about 75 nanometers.

A bipolar junction transistor comprising:

• a semiconductor substrate having a substantially planar surface including a dielectric layer formed on or within said substrate;
• a first epitaxial semiconducting structure including a dopant of a first polarity disposed on said dielectric layer, said first epitaxial semiconducting structure having an area formed in a plane parallel to said substrate of less than about 15,000 square nanometers;
• a second epitaxial semiconducting structure including a dopant of a second polarity formed on said first epitaxial semiconductor structure, said second epitaxial semiconducting structure having an area formed in a plane parallel to said substrate of less than about 15,000 square nanometers;
• a third epitaxial semiconducting structure including a dopant of said first polarity formed on said second epitaxial semiconductor sturcture, said third epitaxial structure having an area formed in a plane parallel to said substrate of less than about 15,000 square nanometers;
• and
• an electrically conductive layer forming an ohmic contact to a portion of said second epitaxial semiconducting structure, and said electrically conductive layer forming a Schottky barrier to a portion of either said first or said third epitaxial semiconducting structures, whereby a Schottky diode clamped bipolar junction transistor is formed.

A bipolar junction transistor, comprising:

• a semiconductor substrate having a substantially planar surface including a dielectric layer formed on said substrate
• an epitaxial semiconducting structure formed on said dielectric layer, said epitaxial structure having an area having at least one lateral dimension less than about 75 nanometers, and forming a base region of the bipolar junction transistor;
• a first polycrystalline semiconducting structure, formed on at least a portion of said epitaxial structure, said first polycrystalline structure having an area having at least one lateral dimension less than about 75 nanometers, and forming an emitter region of the bipolar junction transistor;
• and
• a second polycrystalline semiconducting structure formed on at least a portion of said epitaxial structure, said second polycrystalline structure having an area having at least one lateral dimension less than about 75 nanometers, and forming a collector region of the bipolar junction transistor.

A diode array, comprising:

• a silicon semiconductor wafer;
• an insulating layer disposed over said silicon wafer;
• a plurality of epitaxial semiconducting structures having an area having at least one lateral dimension less than about 75 nanometers, said plurality of epitaxial structures disposed over said insulating layer;
• and
• a plurality of polycrystalline semiconducting structures having an area having at least one lateral dimension less than about 75 nanometers, said plurality of polycrystalline structures in contact with said plurality of epitaxial structures, forming an array of semiconducting junctions.

A semiconductor device comprising:

• a substrate;
• an epitaxial semiconducting structure formed on said substrate;
• a polycrystalline semiconducting structure;
• and
• means for forming a first semiconducting junction between said epitaxial semiconductor structure and said polycrystalline semiconducting structure, said semiconducting junction having an area having at least one lateral dimension less than about 75 nanometers.

A method for forming nanoscale semiconductor junctions comprising:

• creating an epitaxial semiconducting layer including a dopant of a first polarity formed on a complementary doped semiconductor substrate;
• creating an imprint layer on said epitaxial semiconducting layer;
• urging a nanoimprinter toward said imprint layer;
• removing selective portions of said epitaxial semiconducting layer
• forming an epitaxial semiconducting structure having an area having at least one lateral dimension less than about 75 nanometers;
• creating a dielectric layer over said epitaxial semiconducting structure;
• co-planarizing said dielectric layer to substantially the same thickness as said epitaxial semiconducting structure;
• creating a polycrystalline semiconducting layer including a dopant of a second polarity over said epitaxial semiconducting layer and said dielectric layer;
• removing selective portions of said polycrystalline semiconducting layer;
• and
• forming a polycrystalline semiconducting structure having an area having at least one lateral dimension less than about 75 nanometers by selectively removing portions of said polycrystalline semiconducting layer.

A method for forming nanoscale semiconductor junctions comprising:

• creating an imprint layer on an epitaxial semiconducting layer;
• urging a nanoimprinter toward said imprint layer;
• removing selective portions of said epitaxial semiconducting layer;
• forming an epitaxial semiconducting structure having an area having at least one lateral dimension less than about 75 nanometers;
• and
• forming a first semiconducting junction having an area having at least one lateral dimension less than about 75 nanometers.

A method for forming nanoscale junctions comprising:

• creating a doped epitaxial silicon layer, which has a thickness less than about 75 nanometers, on a doped silicon wafer;
• urging a nanoimprinter toward an imprint layer
• removing selective portions of said doped epitaxial silicon layer;
• forming a semiconductor junction between said doped silicon wafer and said epitaxial silicon layer having an area having at least one lateral dimension less than about 75 nanometers;
• forming a planarizing dielectric layer over said doped epitaxial silicon structure;
• co-planarizing said planarizing dielectric layer to substantially the same thickness as said doped epitaxial silicon structure;
• creating a second semiconducting layer over said epitaxial silicon structure and said planarizing dielectric layer, said semiconducting layer having a dopant opposite in polarity to said epitaxial silicon layer;
• urging a nanoimprinter toward a second imprint layer;
• removing selective portions of said second semiconducting layer;
• and
• forming a second semiconductor junction between said doped epitaxial layer and said second semiconducting layer having an area having at least one lateral dimension less than about 75 nanometers.