US 2004/0063264 A1Published application

Method of forming a high performance and low cost CMOS device

AssigneeChartered Semiconductor Manufacturing Ltd.

InventorsJia Zhen Zheng, Soh Yun Siah, Liang Choo Hsia, Eng Hua Lim, Simon Chooi, Chew Hoe Ang

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Abstract

A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component. After formation of a block out shape in a PMOS region of the CMOS device, a high angle implantation procedure is used to form a P type halo region in a top portion of the NMOS region, followed by another implantation procedure performed at lower implant angles, resulting in an N type LDD region in a portion of the NMOS region underlying the thicker horizontal spacer component, and resulting in an N type heavily doped source/drain region in a portion of the NMOS underlying the thinner horizontal spacer component. Another block out shape, and another series of similar implantation procedures is performed to create the halo, LDD and source/drain regions in the PMOS region. After formation of a photoresist block out shape on specific CMOS regions, a composite insulator spacer is formed on the sides of gate structures not covered by the photoresist shape, followed by formation of metal silicide on the gate structures and source/drain regions not covered by the photoresist block out shape.

Claims27

Dependent claims

A method of fabricating a complimentary metal oxide semiconductor (CMOS) device on a semiconductor substrate, comprising the steps of:

providing a first device region of said semiconductor substrate to accommodate a first conductivity type device, and providing a second device region of said semiconductor substrate to accommodate a second conductivity type device;
forming gate structures on an underlying gate insulator layer in said first device region, and in said second device region;
forming insulator structures comprised of a thick insulator component located on the sides of said gate structures and on a first portion of the semiconductor substrate located adjacent to said gate structure, and comprised of a thin insulator component located on a second portion of said semiconductor substrate in turn located adjacent to the thick insulator component overlying said first portion of said semiconductor substrate;
performing a first series of ion implantation procedures in said first device region to form a first halo region of a first conductivity type in said first portion of said semiconductor substrate, in said second portion of said semiconductor substrate, and in a portion of said semiconductor substrate underlying an edge of said gate structure, and to form a first lightly doped source/drain (LDD) region of a second conductivity type in a top portion of said halo region underlying said thick insulator component, and to form a first heavily doped source/drain region of a second conductivity type in a top portion of said halo region located underlying said thin insulator component located overlying said second portion of said semiconductor substrate;
performing a second series of ion implantation procedures in said second device region to form a second halo region of a second conductivity type in a first portion of said semiconductor substrate, in a second portion of said semiconductor substrate, and in a portion of said semiconductor substrate underlying an edge of said gate structure, and to form a second lightly doped source/drain (LDD) region of a first conductivity type in a top portion of said halo region underlying said thick insulator component, and to form a second heavily doped source/drain region of a first conductivity type in a top portion of said halo region underlying said thick insulator component located overlying said second portion of said semiconductor substrate;
forming insulator shapes on said insulator structure located in said first device region resulting in a composite insulator spacer on gate structure exposing top surface of said gate structure and exposing top surface of said second heavily doped source/drain region;
and
forming metal silicide on exposed said top surface of said gate structure and on top surface of said first heavily doped source/drain region.

5 more elements

15 A method of fabricating a CMOS device on a semiconductor substrate, comprising the steps of:

providing a first portion of said semiconductor substrate as an N channel metal oxide semiconductor (NMOS) region, to accommodate an NMOS device, and providing a second portion of said semiconductor substrate as a P channel metal oxide semiconductor (PMOS) region to accommodate a PMOS device;
growing a silicon dioxide gate insulator on said semiconductor substrate;
forming gate structures on said silicon dioxide gate insulator layer;
depositing a silicon oxide layer;
depositing a first silicon nitride layer;
performing a first anisotropic reactive ion etch (RIE), procedure to form first composite insulator spacers on the sides of said gate structures, comprised of first silicon nitride shapes on underlying thick silicon oxide shapes, overlying first portions of said semiconductor substrate, and with thin silicon oxide shapes, not covered by said gate structures or by said first composite insulator spacers, formed overlying second portions of said semiconductor substrate;
removing said first silicon nitride shapes resulting in an L shaped silicon oxide spacer comprised of said thick silicon oxide shape on sides of said gate structure and overlying said first portions of said semiconductor substrate, and with said L shaped silicon oxide spacer comprised of said thin silicon oxide shapes overlying said second portions of said semiconductor substrate;
forming a first block out shape in said PMOS region;
performing a first series of ion implantation procedures in said NMOS region to form a P type halo region in said first portion of said semiconductor substrate, in said second portion of said semiconductor substrate, and in a third portion of said semiconductor substrate located underlying an edge of said gate structure, and to form an N type lightly doped source/drain (LDD) region in a top portion of said P type halo region underlying said thick silicon oxide shape, and to form an N type heavily doped source/drain region in a top portion of said P type halo region located underlying said thin silicon oxide shape;
forming a second block out shape in said NMOS region;
performing a second series of ion implantation procedures in said PMOS region device region to form an N type halo region in a first portion of said semiconductor substrate, in a second portion of said semiconductor substrate, and in a third portion of said semiconductor substrate underlying an edge of said gate structure, and to form a P type LDD region in a top portion of said N type halo region underlying said thick silicon oxide shape, and to form a P type heavily doped source/drain region in a top portion of said N type halo region located underlying said thin silicon oxide shape;
depositing a second silicon nitride layer;
performing a second anisotropic RIE procedure resulting in a second composite insulator spacer in said NMOS region, comprised of said second silicon nitride shapes on said thick silicon oxide shapes of said L shaped silicon oxide spacer, and exposing top surface of said N type heavily doped source/drain region, while second silicon nitride layer in said PMOS region remains unetched;
and
forming metal silicide on said top surface of said gate structure and on top surface of said N type heavily doped source/drain region, in said NMOS region.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/262,169Filed 1 Oct 2002
Published: 1 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/0229
Having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped…
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions