Method and apparatus for system time clock recovery
AssigneeATI Technologies ULC
InventorWai-Leong Poon
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Abstract
Briefly, a system time clock (STC) recovery apparatus includes an STC counter that receives a program clock reference (PCR) signal. The STC recovery apparatus also includes a phase lock loop that generates an STC signal having an STC frequency and a fractional divider that generates a modified STC signal by adjusting the STC frequency of the STC signal such that the modified STC signal is provided to the STC counter. The STC clock recovery apparatus further includes a register, such as any suitable memory, which stores a target frequency value and a source frequency value. The target frequency value is the value of the target frequency for the modified STC signal and the source frequency value is the value of the frequency of the STC signal from the phase lock loop.
Claims21
An apparatus for system time clock (STC) recovery comprising:
- an STC counter that receives a program clock reference signal;
- a phase lock loop that generates an STC signal having an STC frequency;
- and
- a fractional divider that generates a modified STC signal by adjusting the STC frequency of the STC signal such that the modified STC signal is provided to the STC counter.
An apparatus for system time clock (STC) recovery comprising:
- an STC counter that receives a program clock reference signal;
- a signal frequency adjustor that receives a system timing signal and generates an STC signal having an STC frequency, the signal adjustor includes:
- a first frequency adjustor that receives the system timing signal;
- a phase lock loop coupled to the first frequency adjustor;
- a feedback frequency adjustor;
- and
- a second frequency adjustor such that the phase lock loop, using the first frequency adjustor, the feedback frequency adjustor and the second frequency adjustor generates the STC signal having the STC frequency;
- and
- a fractional divider that generates a modified STC signal by adjusting the STC frequency of the STC signal such that the modified STC signal is provided to the STC counter.
A method for system time clock (STC) recovery comprising:
- receiving an STC signal having an STC frequency;
- generating a modified STC signal by adjusting the STC frequency of the STC signal by a factor of a target frequency value divided by a source frequency value;
- and
- providing the modified STC signal to an STC counter.
A method for video graphics decoding comprising:
- receiving a system timing signal from a voltage source;
- generating a system time clock (STC) signal having an STC frequency using a phase lock loop;
- receiving a program clock reference signal;
- generating a modified STC signal by adjusting the STC frequency of the STC signal by a factor of a target frequency value divided by a source frequency value;
- and
- providing the modified STC signal to an STC counter.
Dependencies are inferred from the claim text.