System and method for clock synchronization of multi-channel baud-rate timing recovery systems

A clock control circuit for use in a multi-channel baud-rate timing recovery loop, comprising

• first circuitry for generating a proportional output responsive to an input from at least one phase detector;
• second circuitry for generating an integrating output responsive to an input from the at least one phase detector;
• a plurality of resettable phase error integrators connected to the first circuitry and the second circuitry for accumulating outputs until a programmable threshold is reached, said plurality of resettable phase error integrators outputting a pulse and resetting responsive to reaching said programmable threshold level;
• and
• a plurality of Mod-N integrators for generating a clock control signal to select an N sampling phase of an N-tap digitally controlled oscillator responsive to outputs of the plurality of resettable phase error integrators.

12 An N-channel baud-rate timing recovery loop, comprising.

• at least one A/D converter;
• at least one signal processing circuit and one phase detector connected to the at least one A/D converter,
• a slave control circuit responsive to a phase error signal from the at least one phase detector for generating at least one clock control signal, wherein said slave control circuit propagates adjustments required for frequency correction in a synchronous fashion across all of the N-channels, and
• at least one oscillator responsive to the at least one clock control signal for generating a clock signal for an A/D converter.

The N-channel baud-rate timing recovery loop of claim 12, wherein the slave control circuit further comprises:

• a plurality of first amplifiers each generating proportional outputs responsive to input from a phase detector;
• a plurality of first resettable phase error integrators each connected to one of the plurality of first amplifiers for accumulating proportional outputs until a programmable threshold is reached, said resettable phase error integrators outputting a pulse and resetting responsive to reaching said programmable threshold,
• at least one second amplifier for generating a second output responsive to input from at least one phase detector,
• an integrator for integrating the second output to generate an integrating output proportional to a frequency offset;
• a second resettable phase error integrator for accumulating integrating outputs until a second programmable threshold is reached, said second resettable phase error integrators outputting a pulse and resetting responsive to reaching said second programmable threshold;
• and
• a plurality of Mod-N integrators for generating a clock control signal to select an N sampling phase of N-tap frequency and phase corrected digitally controlled oscillators responsive to outputs of the plurality of first resettable phase error integrators and the second resettable phase error integrator.

The N-channel baud-rate timing recovery loop of claim 12, wherein the slave control circuit further comprises:

• first circuitry for generating a proportional output responsive to an input from at least one phase detector,
• second circuitry for generating an integrating output responsive to an input from at least one phase detector;
• a plurality of resettable phase error integrators connected to the first circuitry and the second circuitry for accumulating proportional outputs or integrating outputs until a programmable threshold is reached, said plurality of resettable phase error integrators outputting a pulse and resetting responsive to reaching said threshold level;
• and
• a plurality of Mod-N integrators for generating a clock control signal to select an N sampling phase of an N-tap digitally controlled oscillator responsive to outputs of the plurality of resettable phase error integrators.