Method and system for improved phase tracking
AssigneeIntel Corporation
InventorsSanjay Dabral, Chamath Abhayagunawardhana, Ken Drottar
Life of this patent
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Abstract
A method and system for improved phase tracking in communication systems is disclosed. In one embodiment, a method, comprises identifying a slow-time varying phase drift on a link by counting long term beats; calibrating an interpolator with the phase drift; predicting a future phase drift; and updating the interpolator periodically with the future phase drift prediction.
Claims23
1). A method, comprising:
- identifying a slow-time varying phase drift on a link by counting long term beats;
- calibrating an interpolator with the phase drift;
- predicting a future phase drift;
- and
- updating the interpolator periodically with the future phase drift prediction.
2). The method of claim 1, further comprising:
- initializing timing;
- and
- framing.
3). The method of claim 2, wherein predicting a future phase drift comprises:
- generating a vote that indicates if the interpolator should shift phase up or down;
- providing the vote to a loop filter that accumulates one or more additional votes, until a predetermined threshold is met;
- providing filter signals from the loop filter to a direction predictor that predicts which direction the interpolator should shift;
- providing a freeze signal to a drift predictor that predicts the drift compensation needed by the interpolator;
- and
- providing the filter signals, a drift compensation signal from the drift predictor, to an interpolator controller that generates a future phase drift prediction.
4). The method of claim 3, wherein the link connects two micro chips.
5). The method of claim 4, wherein the two micro chips are part of a plesiochronous system.
6). A computer-readable medium having stored thereon a plurality of instructions, said plurality of instructions when executed by a computer, cause said computer to perform:
- identifying a slow-time varying phase drift on a link by counting long term beats;
- calibrating an interpolator with the phase drift;
- predicting a future phase drift;
- and
- updating the interpolator periodically with the future phase drift prediction.
7). The computer-readable medium of claim 7, having stored thereon additional instructions, said additional instructions when executed by a computer, cause said computer to further perform:
- initializing timing;
- and
- framing.
8). The computer-readable medium of claim 7, having stored thereon additional instructions, said additional instructions when executed by a computer for predicting a future phase drift, cause said computer to further perform:
- generating a vote that indicates if the interpolator should shift phase up or down;
- providing the vote to a loop filter that accumulates one or more additional votes, until a predetermined threshold is met;
- providing filter signals from the loop filter to a direction predictor that predicts which direction the interpolator should shift;
- providing a freeze signal to a drift predictor that predicts the drift compensation needed by the interpolator;
- and
- providing the filter signals, a drift compensation signal from the drift predictor, to an interpolator controller that generates a future phase drift prediction.
9). The computer-readable medium of claim 8, wherein the link connects two micro chips.
10). The computer-readable medium of claim 9, wherein the two micro chips are part of a plesiochronous system.
11). A system, comprising:
- a first micro chip;
- a second micro chip having a link to the first micro chip;
- and
- a phase tracker using fine interpolation connected to the first and second micro chips.
12). The system of claim 11, wherein the phase tracker comprises:
- a phase comparator;
- a loop filter connected to the comparator;
- a drift predictor connected to the loop filter;
- a direction predictor connected to the drift predictor;
- an interpolator controller connected to the loop filter, the drift predictor and the direction predictor;
- and
- an interpolator connected to the interpolator controller and the comparator.
13). The system of claim 12, wherein the drift predictor comprises:
- two or more flip-flops;
- and
- an OR gate connected to the two or more flip-flops.
14). The system of claim 12, wherein the direction predictor comprises:
- two or more counters;
- and
- a comparator connected to the two or more counters.
15). The system of claim 14, wherein the loop filter comprises:
- an accumulator;
- and
- a state machine.
16). A system, comprising:
- means for comparing phase of a sampling clock and a data clock;
- means for accumulating one or more votes;
- means for comparing the votes to a predetermined threshold value;
- means for predicting a direction in which a phase tracking interpolator should be adjusted;
- means for predicting a drift compensation;
- means for controlling an interpolator;
- and
- means for generating a new sampling clock with a phase matching the data clock.
17). The system of claim 16, wherein the means for predicting a drift compensation comprises:
- one or more means for latching votes;
- and
- means for ORing the votes.
18). The system of claim 17, wherein the means for predicting a direction comprises:
- one or more means for counting;
- and
- means for comparing values from the means for counting.
19). An apparatus, comprising:
- a first micro chip;
- a second micro chip having a link to the first micro chip;
- and
- a phase tracker using fine interpolation connected to the first and second micro chips.
20). The apparatus of claim 19, wherein the phase tracker comprises:
- a phase comparator;
- a loop filter connected to the comparator;
- a drift predictor connected to the loop filter;
- a direction predictor connected to the drift predictor;
- an interpolator controller connected to the loop filter, the drift predictor and the direction predictor;
- and
- an interpolator connected to the interpolator controller and the comparator.
21). The apparatus of claim 20, wherein the drift predictor comprises:
- two or more flip-flops;
- and
- an OR gate connected to the two or more flip-flops.
22). The apparatus of claim 20, wherein the direction predictor comprises:
- two or more counters;
- and
- a comparator connected to the two or more counters.
23). The apparatus of claim 22, wherein the loop filter comprises:
- an accumulator;
- and
- a state machine.