US 2004/0062096 A1 · Rapidly testable semiconductor memory device

Abstract

A semiconductor memory device has an array of memory cells, an array of sense amplifiers selected at least two at a time by column lines, data bus lines that receive data read from the memory cell array by the selected sense amplifiers, a decision circuit that compares data read by two of the selected sense amplifiers, and an input-output buffer. Normally, the input-output buffer receives and outputs data from one or more of the data bus lines. In a test output mode, the input-output buffer receives and outputs comparison result data from the decision circuit. In a semiconductor memory device with multiple memory cell arrays, this arrangement enables data read from different memory cells in the same memory cell array to be compared, so that redundancy repair can be carried out efficiently.

Claims19

Dependent claims

A semiconductor memory device operable in a normal output mode and a test output mode, comprising:

a first array of memory cells;
a first array of sense amplifiers for reading data from the first array of memory cells;
a plurality of column lines coupled to the first array of sense amplifiers, each column line selecting at least two of the sense amplifiers in the first array of sense amplifiers;
a plurality of data bus lines receiving the data read by the selected sense amplifiers in the first array of sense amplifiers;
a first decision circuit receiving and comparing data read by two of the selected sense amplifiers in the first array of sense amplifiers and generating comparison result data;
and
a first input-output buffer receiving data from at least one of the data bus lines in the normal output mode, receiving the comparison result data from the first decision circuit in the test output mode, and providing external output of the received data.

4 more elements

A semiconductor memory device operable in a normal output mode and a first test output mode, comprising:

a plurality of column signal lines;
a plurality of arrays of sense amplifiers, the sense amplifiers in each array being selectable at least two at a time by the column signal lines;
a plurality of memory cell arrays interspersed among the sense amplifier arrays so that data stored in each memory cell array are read by sense amplifiers in two adjacent arrays of sense amplifiers;
a plurality of data bus lines for receiving data read from the memory cell arrays by the sense amplifiers in the sense amplifier arrays;
a plurality of primary decision circuits connected to respective arrays of sense amplifiers, each primary decision circuit comparing data read by two of the selected sense amplifiers in the connected one of the arrays of sense amplifiers and generating first comparison result data;
a plurality of secondary decision circuits for comparing the first comparison result data generated by adjacent pairs of the primary decision circuits and generating second comparison result data;
and
a plurality of input-output buffers receiving data from the data bus lines in the normal output mode, receiving the second comparison result data from the secondary decision circuits in the first test output mode, and providing external output of the received data.

5 more elements

Dependencies are inferred from the claim text.

Rapidly testable semiconductor memory device

Life of this patent

Rapidly testable semiconductor memory device

Life of this patent

Abstract

Claims19