Method for identification of faulty or weak functional logic elements under simulated extreme operating conditions
AssigneeArtisan Components, Inc.
InventorsMark Templeton, Dhrumil Gandhi
Life of this patent
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Abstract
A method for testing a circuit is provided. The method includes providing a normal internal clock signal for use in accessing functional logic, where the functional logic has access to redundant functional logic during normal operation. The method then applies a stress clock signal to the functional logic, and each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. Based on the applied stress clock signal, the method identifies logic elements of the functional logic that fail to operate as intended.
Claims18
A method for identifying faulty functional logic, comprising the operations of:
- providing a normal internal clock signal for use in accessing functional logic, the functional logic having access to redundant functional logic during normal operation;
- and
- performing a test on the functional logic using a stress clock signal, wherein each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal, wherein functional logic elements that fail the test using the stress clock signal are identified as non-usable functional logic elements.
A method for identifying faulty functional logic, comprising the operations of:
- providing a normal internal clock signal for use in accessing functional logic, the functional logic having access to redundant functional logic during normal operation;
- and
- applying a test on the functional logic using a stress clock signal, wherein each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal;
- determining if logic elements of the functional logic are faulty based on the use of the stress clock signal;
- and
- re-routing signals previously routed through the faulty logic elements through the redundant functional logic.
A method for testing a circuit, comprising:
- providing a normal internal clock signal for use in accessing functional logic, the functional logic having access to redundant functional logic during normal operation;
- and
- applying a stress clock signal to the functional logic, each pulse of the stress clock signal being of a shorter duration than each pulse of the normal internal clock signal;
- and
- identifying logic elements of the functional logic that fail to operate as intended when operated using the stress clock signal.
Dependencies are inferred from the claim text.