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AssigneeTexas Instruments Incorporated
InventorsVikas K. Agrawal, Bryan D. Sheffield, Stephen W. Spriggs
Estimating the term…
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
A memory circuit, comprising:
The memory circuit of claim 9, wherein a rate in which the diode is decoupled from the input of the second inverter decreases when the supply voltage decreases, thereby slowing the rate by which the output of the second inverter transitions from high to low when the supply voltage decreases.
In combination with a memory array comprising a plurality of memory cells, a memory control circuit operable to generate one or more control signals for initiation of memory operations associated with the memory array, the control circuit comprising a cycle ready circuit operable to generate a cycle ready strobe signal for initiating a next memory operation after an initial memory operation based on identification of a completion of the initial memory operation.
Dependencies are inferred from the claim text.