Memory device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorMasaya Sumita
Life of this patent
Estimating the term…
Abstract
There are provided at least one read word line 15, 16 and 17 for transmitting a read control signal to a memory cell, at least one read bit line 18, 19 and 20 for transmitting information of the memory cell to an outside according to activation of the read control signal corresponding to the read word line, at least one write word line 11 and 12 for transmitting a write control signal to the memory cell, and at least one write bit line 13 and 14 for transmitting external information to the memory cell according to activation of the write control signal corresponding to the write word line, wherein the read bit line and the write bit line are provided as alternately as possible and the read control signal and the write control signal are controlled so as not to be activated at the same time.
Claims25
A memory device comprising at least one read control signal line for transmitting a read control signal to a memory cell, at least one read signal line for transmitting information of the memory cell to an outside according to activation of the read control signal corresponding to the read control signal line, at least one write control signal line for transmitting a write control signal to the memory cell, and at least one write signal line for transmitting external information to the memory cell according to activation of the write control signal corresponding to the write control signal line,
- wherein the read signal line and the write signal line are alternately provided and the read control signal and the write control signal are controlled so as not to be activated at the same time.
A memory device wherein a storage element in a memory cell is constituted by first and second inverting logic gates, a reset signal line is connected to a first source of the first inverting logic gate, a reset signal to be sent to the reset signal line is fixed to be inactive during a reading and writing operation of the memory cell, and the reset signal is activated to set a state of the storage element to have a desirable value for a period other than the reading and writing operation.
A memory device wherein a storage element in a memory cell is constituted by first and second inverting logic gates, a NOT signal of AND of a write control signal and a write signal is connected to a first source of a transistor constituting the first inverting logic gate, an AND signal of a write control signal and an inverted write signal is connected to a second source of the transistor constituting the first inverting logic gate, a NOT signal of AND of the write control signal and the inverted write signal is connected to a first source of a transistor constituting the second inverting logic gate, and an AND signal of the write control signal and the write signal is connected to a second source of the transistor constituting the second inverting logic gate.
Dependencies are inferred from the claim text.