Semiconductor memory device based on dummy-cell method
AssigneeFujitsu Limited
InventorsMasato Takita, Shinichi Yamada, Masato Matsumiya
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Abstract
A semiconductor memory device includes a plurality of bit line pairs, each of which includes a first bit line and a second bit line, a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors, a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential, a sense amplifier which amplifies a potential difference between the first bit line and the second bit line, and a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.
Claims9
A semiconductor memory device, comprising:
- a plurality of bit line pairs, each of which includes a first bit line and a second bit line;
- a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors;
- a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential;
- a sense amplifier which amplifies a potential difference between the first bit line and the second bit line;
- and
- a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.
Dependencies are inferred from the claim text.