Nonvolatile memory device with configuration switching the number of memory cells used for one-bit data storage
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
Estimating the term…
Abstract
A memory cell array has a plurality of memory cells and dummy memory cells. A column select portion switches access control to a memory cell in accordance with a mode control signal. The column select portion selects one memory cell column to connect a first or second bit line connected with one selected memory cell and first and second reference data lines connected with the dummy memory cells to a data read circuit in a first mode. The column select portion connects the first and second bit lines respectively connected to paired two selected memory cells storing data complimentary to each other to the data read circuit in a second mode.
Claims18
A nonvolatile memory device comprising:
- a memory cell array having a plurality of memory cells arranged in a matrix, each of said plurality of memory cells having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data;
- an access control circuit for switching access to said plurality of memory cells based on an input address between a first mode in which each of said plurality of memory cells stores one-bit data and a second mode in which each pair of two of said plurality of memory cells stores one-bit data;
- a data read circuit performing a data read from a selected portion of said plurality of memory cells that is selected to be accessed by said access control circuit;
- and
- a data write circuit performing a data write into said selected portion of said plurality of memory cells.
A nonvolatile memory device comprising:
- a plurality of memory cells each having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data;
- a plurality of dummy cells provided to be compared with said plurality of memory cells in said reading data and having same characteristic as said plurality of memory cells, wherein
- at least ones of said plurality of dummy cells are respectively set to said first and second states;
- and
- a data read circuit, based on access to a selected memory cell selected to be accessed of said plurality of memory cells and to said plurality of dummy cells, reading said stored data from said selected memory.
A nonvolatile memory device comprising:
- a plurality of memory cell blocks;
- and
- a data read circuit provided to be shared by said plurality of memory cell blocks,
- each of said plurality of memory cell blocks including
- a plurality of memory cells each having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data and
- a plurality of dummy cells provided to be compared with said plurality of memory cells in said reading data and having same characteristics as said plurality of memory cells, wherein
- one of said plurality of memory cells is selected as a read target memory cell from which data is to be read in one of said plurality of memory cell blocks, and
- said data read circuit reads said stored data from said read target memory cell based on respective access to said read target memory cell and to one of said plurality of dummy memory cells included in another one of said plurality of memory cell blocks.
Dependencies are inferred from the claim text.