Bitline equalization system for a DRAM integrated circuit
AssigneeInfineon Technologies North America Corp.
InventorsStephen M. Camacho, Paul E. Brucke
Life of this patent
Estimating the term…
Abstract
A system for pre-charging and equalizing potentials on a bitline pair in a DRAM integrated circuit. The system includes an equalization circuit at one position on the bitline pair and another equalization circuit at another position on the bitline pair. As charge is distributed between the bitlines and to/from the pre-charge potential source through multiple conduction paths, the pre-charge and equalization time of the bitlines is reduced.
Claims14
A bitline equalization system for pre-charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising:
- a first equalization circuit connected between a first position along the bitline and a corresponding first position along the complementary bitline;
- and
- a second equalization circuit connected between a second position along the bitline and a corresponding second position along the complementary bitline, wherein the first position is closer to a beginning of the bitline than the second position, and wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position.
The bitline equalization system of claim 6, wherein the first equalization line and the second equalization line are a shared common equalization line.
A bitline equalization system for pre-charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising:
- means for exchanging charge between the bitline and an equalization potential at a first position along the bitline;
- means for exchanging charge between the complementary bitline and the equalization potential at a corresponding first position along the complementary bitline;
- and
- means for exchanging charge between a second position along the bitline and a corresponding second position along the complementary bitline, wherein the first position is closer to a beginning of the bitline than the second position, and wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position.
A bitline equalization system for pre-charging a bitline and a complementary bitline to an equalization potential in a DRAM integrated circuit, the bitline equalization system comprising:
- a first transistor having a first gate connected to a common equalization line, a first source connected to the first position along the bitline, and a first drain connected to the corresponding first position along the complementary bitline;
- a second transistor having a second gate connected to the common equalization line, a second source connected to the first position along the bitline, and a second drain connected to the equalization potential;
- a third transistor having a third gate connected to the common equalization line, a third source connected to the corresponding first position along the complementary bitline, and a third drain connected to the equalization potential;
- and
- a fourth transistor having a fourth gate connected to the common equalization line, a fourth source connected to the second position along the bitline, and a fourth drain connected to the corresponding second position along the complementary bitline, wherein the first position is closer to a beginning of the bitline than the second position, and wherein the first complementary position is closer to a beginning of the complementary bitline than the second complementary position.
The bitline equalization system of claim 15, further comprising:
- a fifth transistor having a fifth gate connected to the common equalization line, a fifth source connected to the second position along the bitline, and a fifth drain connected to the equalization potential;
- and
- a sixth transistor having a sixth gate connected to the common equalization line, a sixth source connected to the corresponding second position along the complementary bitline, and a sixth drain connected to the equalization potential.
Dependencies are inferred from the claim text.