Frequency multiplier and method of multiplying frequency of external clock signal, data output buffer, and semiconductor device including the frequency multiplier and the data output

A frequency multiplier which receives an external clock signal having a predetermined frequency, multiplies the external clock signal, and outputs the multiplied signal as an internal clock signal, the frequency multiplier comprising:

• a first pulse signal generating circuit which receives a first clock signal and a second clock signal having the same frequency and outputs a first pulse signal having a first pulse width when the level of the first clock signal is greater than the level of the second clock signal;
• a second pulse signal generating circuit which is enabled in response to a first control signal and outputs a second pulse signal having a second pulse width when the level of the reference voltage is greater than the level of the first clock signal;
• a third pulse signal generating circuit which is enabled in response to a second control signal and the reference voltage and outputs a third pulse signal having a third pulse width when the level of the second clock signal is greater than the level of the reference voltage;
• a fourth pulse signal generating circuit which is enabled in response to a second control signal, receives the reference voltage and the second control signal, and outputs a fourth pulse signal having a fourth pulse width when the level of the reference voltage is greater than the level of the second clock signal;
• and
• an OR circuit which receives the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal, and outputs the internal clock signal which is the logical sum of the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal.

A data output buffer of a semiconductor device comprising:

• N flip flops which receive a first clock signal, are connected in series to each other, including a first flip flop that receives data to be output from the semiconductor device, is synchronized with the first clock signal, and outputs the data, and second through Nth flip flops that each receive an output signal of the preceding flip flop in the series, is synchronized with the first clock signal, and outputs the output signal of the preceding flip flop;
• an OR circuit which receives output signals from the N flip flops, logically sums the output signals, and outputs the signal obtained by the summation;
• and
• an output circuit which is synchronized with a second clock signal and outputs the output signal of the OR circuit,
• wherein the clock signal frequency of the first clock signal is N times greater than the clock signal frequency of the second clock signal.

A semiconductor device comprising:

• a frequency multiplier which is placed in an input terminal of the semiconductor device, receives a clock signal having a predetermined frequency, and outputs an internal clock signal having greater frequency than the predetermined frequency;
• and
• a data output buffer which outputs data tested according to data written to test the semiconductor device,
• wherein the frequency multiplier comprises:
• a first pulse signal generating circuit which receives a first clock signal and a second clock signal having the same frequency and outputs a first pulse signal having a first pulse width when the level of the first clock signal is greater than the level of the second clock signal;
• a second pulse signal generating circuit which is enabled in response to a first control signal and outputs a second pulse signal having a second pulse width when the level of the reference voltage is greater than the level of the first clock signal;
• a third pulse signal generating circuit which is enabled in response to a second control signal and the reference voltage and outputs a third pulse signal having a third pulse width when the level of the second clock signal is greater than the level of the reference voltage;
• a fourth pulse signal generating circuit which is enabled in response to a second control signal, receives the reference voltage and the second control signal, and outputs a fourth pulse signal having a fourth pulse width when the level of the reference voltage is greater than the level of the second clock signal;
• and
• an OR circuit which receives the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal and outputs the internal clock signal which is the logical sum of the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal.

A method of multiplying a frequency where a clock signal having a predetermined frequency is received, the received clock signal is multiplied, and the multiplied signal is output as an internal signal, the method comprising:

• generating a first pulse signal, which receives a first clock signal and a second clock signal and which has a first pulse width, when a level of the first clock signal is greater than a level of the second clock signal;
• generating a second pulse signal which is enabled in response to a first control signal, and has a second pulse width, when the level of a received reference voltage is greater than the level of the first clock signal;
• and
• receiving the first pulse signal and the second pulse signal, logically summing the first pulse signal and the second pulse signal, and outputting the signal obtained by the summation as the internal clock signal.

A method of multiplying a frequency where a clock signal having a predetermined frequency is received, the received clock signal is multiplied, and the multiplied signal is output as an internal signal, the method comprising:

• generating a first pulse signal, which receives a first clock signal and a second clock signal which has the same frequency and has a first pulse width, when the level of the first clock signal is greater than the level of the second clock signal;
• generating a second pulse signal which is enabled in response to a first control signal and has a second pulse width, when the level of a received reference voltage is greater than the level of the first clock signal;
• generating a third pulse signal which is enabled in response to the second control signal and the reference voltage and has a third pulse width when a level of the second clock signal is greater than a level of the reference voltage;
• generating a fourth pulse signal which is enabled in response to a second control signal, and has a fourth pulse width, when the level of the reference voltage is greater than the level of the second clock signal;
• and
• receiving the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal and outputting the internal clock signal which is the logical sum of the first pulse, the second pulse signal, the third pulse signal, and the fourth pulse signal.