US 2004/0061558 A1Published application

Phase-locked loop circuit reducing steady state phase error

AssigneeNEC Electronics Corporation

InventorsKeiji Hayashida, Atsushi Hasegawa

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Abstract

A phase-locked loop circuit has a DLL circuit in a stage preceding an analog PLL circuit. The DLL circuit detects a phase difference between a reference clock signal and a feedback signal, changes the detected phase difference to a phase difference increased so as to be greater than a steady state phase error which the analog PLL circuit has, and supplies the resultant phase difference to the analog PLL circuit. While the phase difference between the reference clock signal and the feedback signal is being detected by the DLL circuit, the analog PLL circuit operates to reduce the increased phase difference to the steady state phase error. As a result, the phase difference between the reference clock signal and the feedback signal is reduced to a sensitivity limit of a phase comparator in the DLL circuit.

Claims11

Dependent claims

A phase-locked loop circuit comprising:

a DLL circuit having phase difference detecting means for detecting a phase difference between a reference clock signal and a synchronous clock signal to be supplied to an electronic circuit which operates in synchronization with said synchronous clock signal, and a phase difference changing means for, when a phase difference between the reference clock signal and the synchronous clock signal is detected by said phase difference detecting means, outputting a reference clock delay signal and a synchronous clock delay signal, with a predetermined phase difference being added, to increase the detected phase difference between the reference clock signal and the synchronous clock signal;
and
a analog PLL circuit being supplied with said reference clock delay signal and said synchronous clock delay signal from said phase difference changing means, controlling the phase of an output control signal to synchronize said synchronous clock delay signal with said reference clock delay signal, and supplying the output control signal as said synchronous clock signal to said electronic circuit.

A phase-locked loop circuit comprising:

an analog PLL circuit for comparing the phase of a first signal with the phase of a second signal and outputting a third signal;
and
a DLL circuit being supplied with a reference signal and said third signal as a feedback signal, comparing the phase of said reference signal with the phase of said feedback signal, and outputting said first signal and said second signal based on a result of comparison between the phase of said reference signal and the phase of said feedback signal.

Dependencies are inferred from the claim text.

Facts

Application: 10/664,884Filed 22 Sep 2003
Priority: JP 2002-28184226 Sep 2002
Published: 1 Apr 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03L 7/081
Details of the phase-locked loop: provided with an additional controlled phase shifter
H03L 7/07
Using a reference signal applied to a frequency- or phase-locked loop: using several loops, e.g. for redundant clock signal generation
H03L 7/087
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using at least two…
H03L
Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or