Timing generator with low delay multiplexer

A timing generator for use in a semiconductor tester, the timing generator including:

• a delay line having a plurality of delay elements with respective phase-shifted outputs;
• a multiplexer having a plurality of inputs for receiving the phase shifted outputs, and an output, the multiplexer further including a plurality of switch circuits corresponding to the input circuits and disposed between each input circuit and the output to selectively isolate each input circuit from the output;
• and
• phase detection circuitry for detecting the phase shift between the multiplexer output and a reference signal.

A method of selecting a single timing signal from a plurality of timing signals for presentation at an output, the method comprising the steps:

• providing the plurality of timing signals at a plurality of input circuits;
• isolating the plurality of input circuits from the output with a plurality of switching circuits;
• and
• activating one of the plurality of input circuits while simultaneously switching a corresponding one of the plurality of switching circuits to couple the activated input circuit to the output.