Clock reproduction circuit
AssigneeTOA Corporation
InventorKen?apos;ichi Ejima
Life of this patent
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Abstract
A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.
Claims3
A clock reproducing circuit comprising:
- a master clock signal source for generating a master clock signal having a period equal to 1/N-th times as large as one bit period of received data, where N is a positive integer;
- a modulo-N counter for counting said master clock signal;
- edge detecting means for detecting transitions of said received data from a first level to a second level or from the second level to the first level;
- a resetting counter for counting said master clock signal, and resetting said modulo-N counter when a count in said resetting counter becomes a number determined based on said number N and a predetermined number equal to or larger than two (2) during a time interval during which said predetermined number of edge representative signals occur;
- and
- clock generating means for generating a clock signal in accordance with the count in said modulo-N counter.
Dependencies are inferred from the claim text.