Flip-flop circuit for use in electronic devices

A digital flip-flop circuit, comprising:

• a data node for receiving a data signal;
• a clock node for receiving a clock signal;
• a first control node, having a state determined by the state of the data signal for an interval following a state transition of the clock signal, for controlling a first output transistor;
• a second control node, distinct from the first control node and having a state determined by the state of the data signal for an interval following a state transition of the clock signal, for controlling a second output transistor;
• wherein turning on the first output transistor during the interval pulls the output to a first logical state and turning on the second output transistor during the duration pulls the output to a second logical state.

An integrated circuit comprising a plurality of circuits fabricated on a semiconductor substrate, wherein the plurality of circuits includes at least one flop flip circuit, the flip-flop circuit comprising:

• a clock node for receiving a clock signal and a data node for receiving a data signal;
• a first output transistor comprising a source/drain terminal connected to the output node, wherein the first output transistor turns on to bring the output to a first state;
• a second output transistor having opposite conductivity type of the first output transistor and having a source/drain/terminal connected to the output node wherein the second output transistor turns on to bring the output node to a second state;
• a first control node connected to the gate of the first output transistor, wherein the state of the control node is determined by the clock signal and the data signal;
• and
• a second control node, decoupled from the first control node, and connected to a gate terminal of the first output transistor.