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US 2004/0061526 A1Published application
Cascode SSTL output buffer using source followers
AssigneeSun Microsystems, Inc.
InventorsBrian W. Amick, Lynn A. Warriner, Claude R. Gauthier, Tri K. Tran
Life of this patent
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Abstract
A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.
Claims26
An integrated circuit, comprising:
- a biasing circuit arranged to generate a first bias signal;
- a source follower circuit operatively connected to the first bias signal, wherein the source follower circuit is arranged to generate a second bias signal dependent on the first bias signal;
- and
- a cascode circuit operatively connected to the second bias signal, wherein the cascode circuit is arranged to generate an output signal dependent on the second bias signal and an input signal.
1 more element
A method for performing a stub series termination logic operation, comprising:
- generating a first bias signal dependent on a power supply voltage potential;
- generating a second bias signal dependent on the first bias signal;
- and
- generating an output signal dependent on the second bias signal and an input signal, wherein a maximum voltage potential of the output signal is greater than a voltage potential range of the input signal.
1 more element
An integrated circuit, comprising:
- means for generating a first bias signal;
- means for generating a second bias signal dependent on the first bias signal;
- and
- means for outputting an output signal dependent on the second bias signal and an input signal to the means for outputting the output signal, wherein a maximum voltage potential of the output signal is greater than a voltage potential range of the input signal.
1 more element
An integrated circuit, comprising:
- a biasing circuit arranged to generate a first bias signal and a second bias signal;
- a first source follower circuit operatively connected to the first bias signal, wherein the first source follower circuit is arranged to generate a third bias signal dependent on the first bias signal;
- a second source follower circuit operatively connected to the second bias signal, wherein the second source follower circuit is arranged to generate a fourth bias signal dependent on the second bias signal;
- a first cascode circuit operatively connected to the third bias signal, wherein the first cascode circuit is arranged to pull up an output signal dependent on the third bias signal and an input signal;
- and
- a second cascode circuit operatively connected to the fourth bias signal, wherein the second cascode circuit is arranged to pull down the output signal dependent on the fourth bias signal and the input signal.
3 more elements
Dependencies are inferred from the claim text.