Digital level shifter with reduced power dissipation and false transmission blocking

A digital level shift circuit for providing level shifted output signals, the circuit comprising:

• first and second n-channel devices that make output transitions in response to turn-on signals;
• each turn-on signal turning on one of the n-channel devices to make an output transition;
• the first and second n-channel devices not receiving concurrent turn-on signals;
• first and second p-channel devices that make output transitions in response to turn-on signals;
• each turn-on signal turning on one of the p-channel devices to make an output transition;
• the first and second p-channel devices not receiving concurrent turn-on signals;
• and
• sense/prevent circuitry that senses when current greater than a threshold flows through both of the first and second devices of one channel type and, in response, prevents output transitions from being made.

A digital level shift circuit for providing level shifted output signals, the circuit comprising:

• first and second n-channel devices that make output transitions in response to turn-on signals;
• each turn-on signal turning on one of the n-channel devices to make an output transition;
• the first and second n-channel devices not receiving concurrent turn-on signals;
• first and second p-channel devices that make output transitions in response to turn-on signals;
• each turn-on signal turning on one of the p-channel devices to make an output transition;
• the first and second p-channel devices not receiving concurrent turn-on signals;
• and
• control circuitry that controls when each device receives its turn-on signals;
• the control circuitry including:
• feedback circuitry that obtains a feedback signal for each device indicating that the device has made an output transition and that stops the device's turn-on signal in response to the feedback signal;
• and
• sense/prevent circuitry that senses when current above a threshold flows through both of the first and second devices of one channel type and, in response, prevents output transitions from being made.