Time limit function utilization
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Watanabe, Kazuya Matsuzawa, Riichiro Shirota
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Abstract
A time limit function utilization apparatus includes a first function block, a second function block, a signal line which connects the first and second function blocks and allows using a desired function that is generated by accessing the first and second function blocks with each other, and a semiconductor time switch interposed in or connected to the signal line, and disables or enables mutual access between the first and second function blocks upon the lapse of a predetermined time.
Claims31
A time limit function utilization apparatus, comprising:
- a first functional block;
- a second functional block;
- a signal line which connects the first functional block and the second functional block and allows using a desired function that is generated by accessing the first functional block and the second functional block with each other;
- and
- a semiconductor time switch which is interposed in or connected to the signal line, and substantially disables or substantially enables mutual access between the first functional block and the second functional block upon a lapse of a first predetermined time.
A semiconductor integrated circuit comprising:
- an aging circuit configured by parallel-connecting a plurality of aging devices in which an age-based change occurs while a power supply is disconnected, and an output signal sensed in read changes over time;
- and
- a sense circuit comparing the output signal from the aging circuit with a reference signal.
A semiconductor integrated circuit comprising:
- a plurality of aging devices in which an age-based change occurs while a power supply is disconnected, and output signals sensed in read change over time;
- a plurality of operational circuits arranged in correspondence with the plurality of aging devices, and having at least three terminals, respectively, first terminals of which receive the output signals from the plurality of aging devices;
- a plurality of first memory areas electrically connected to second terminals of the plurality of operational circuits, respectively, and each storing at least one predetermined signal level;
- an adder electrically connected to third terminals of the plurality of operational circuits and adding the output signals from the plurality of operational circuits appearing at the third terminals;
- a plurality of circuit breakers which cut off output signals from the plurality of aging devices before the adder receives the output signal on the basis of operational results of the plurality of operational circuits that are obtained by comparing the output signals from the plurality of aging devices with the at least one predetermined signal level;
- a second memory area where a predetermined reference signal is stored, and
- a sense circuit which compares an output signal from the adder and the reference signal stored in the second memory.
Dependencies are inferred from the claim text.