Multi-chip package device including a semiconductor memory chip

A multi-chip package device comprising:

• a plurality of package terminals;
• a semiconductor memory chip having a test circuit, a plurality of address input terminals and a test terminal, the test circuit is enabled when a high voltage level is applied to the test terminal;
• and
• an interface chip connected to the package terminals and the semiconductor memory, the interface chip including,
• a control circuit having a plurality of memory terminals connected to the package terminals and a plurality of address terminals for providing address signals based on signals received from the memory terminals, the control circuit generating a test signal and an enable signal in response to the received signals,
• a high voltage generating circuit connected to the control circuit, the high voltage generating circuit generates a high voltage signal having the high voltage level in response to the enable signal, and
• a transferring circuit connected to the control circuit, the high voltage circuit and the test terminal of the memory chip, the transferring circuit providing the high voltage signal to the memory chip in response to the test signal.

A multi-chip package device comprising:

• a plurality of package terminals;
• a semiconductor memory chip having a test circuit., a plurality of address input terminals, a high voltage input terminal and a test terminal, the test circuit is enabled when a high voltage level is applied to the test terminal;
• and
• an interface chip connected to the package terminals and the semiconductor memory, the interface chip including,
• a control circuit having a plurality of memory terminals connected to the package terminals and a plurality of address terminals for providing address signals based on signals received from the memory terminals, the control circuit generating a test signal and an enable signal in response to the received signals,
• a high voltage generating circuit connected to the control circuit, the high voltage generating circuit generates a high voltage signal having the high voltage level in response to the enable signal, and
• a transferring circuit connected to the control circuit, the high voltage circuit and the high voltage input terminal and the test terminal of the memory chip, the transferring circuit providing the high voltage signal to the memory chip in response to the test signal.