MPEG video bitstream decoder system and method
AssigneeNJR Corporation
InventorsQiong Wu, Kwok K. Chau, Hau-Yung Chen
Life of this patent
Estimating the term…
Abstract
A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.
Claims14
A method for decoding video signals, the method comprising the steps of:
- using an n-bit counter to generate up to n factorial number of distinct bit pattern sequences, wherein n is a positive integer;
- selecting one or more of the n factorial number of distinct bit pattern sequences to create corresponding one or more addressing schemes;
- and
- fetching and storing data that is associated with the video signals using the one or more addressing schemes.
A method for decoding video signals, the method comprising the steps of:
- generating a first bit pattern sequence to be associated with spatial data that is associated with the video signals;
- generating a second bit pattern sequence to be associated with temporal data that is associated with the video signals;
- generating a third bit pattern sequence to be associated with a combined data set comprising the spatial data and the temporal data;
- and
- wherein:
- the first bit pattern sequence , the second bit pattern sequence and the third bit pattern sequence are distinct;
- and
- the first bit pattern sequence , the second bit pattern sequence and the third bit pattern sequence are generated using an n-bit counter.
A computer-readable medium carrying one or more sequences of instructions for decoding video signals in a computer system, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of:
- using an n-bit counter to generate up to n factorial number of distinct bit pattern sequences, wherein n is a positive integer;
- selecting one or more of the n factorial number of distinct bit pattern sequences to create one or more corresponding addressing schemes;
- and
- fetching and storing data that is associated with the video signals using the one or more addressing schemes.
An apparatus for decoding video signals, comprising:
- one or more n-bit counters, wherein each of the one or more n-bit counters can generate up to n factorial number of distinct bit pattern sequences, wherein n is a positive integer;
- and
- one or more multiplexers corresponding to the one or more n-bit counters for selecting one or more of the n factorial number of distinct bit pattern sequences to create one or more corresponding addressing schemes.
Dependencies are inferred from the claim text.