Synchronous mirror delay with reduced delay line taps

A method of synchronizing with a clock signal comprising:

• receiving a first input clock signal having a clock signal time period;
• delaying the first input clock signal a first time period, where the first time period is a static component;
• delaying the first input clock signal a second time period, where the second time period is equivalent to a real data path;
• measuring a remaining time period of the first input clock signal upon receiving a second input clock signal;
• delaying the second input clock signal the first time period to produce a delayed second input clock signal;
• and
• adding the remaining time period of the first input clock signal to the delayed second input clock signal.

A method of synchronizing with a clock signal comprising:

• receiving a clock signal having sequential first and second clock signal time periods;
• delaying the first clock signal time period a first time delay;
• delaying the first clock signal time period a second time delay equal to a real data path;
• measuring a remaining component of the first clock signal time period upon receiving the second clock time signal period;
• reproducing the remaining component of the first clock signal time period;
• merging the reproduced remaining component of the clock signal time period to the second clock signal time period to produce a merged clock signal time period;
• and
• delaying the merged clock signal time period the first time delay.

An SMD circuit comprising:

• a clock source;
• a first delay segment coupled to the clock source;
• a forward delay line coupled to the first delay segment;
• an SMD control circuit coupled to the forward delay line and to the clock source;
• and
• a backward delay line coupled to the clock source, the SMD control circuit, and coupled to a second delay segment.

An integrated circuit comprising:

• a clock input buffer coupled to receive a clock signal with a time period;
• a first delay segment coupled to the clock input buffer;
• a forward delay line coupled to the first delay segment;
• an SMD control circuit coupled to the forward delay line and to the clock input buffer;
• and
• a backward delay line coupled to the SMD control circuit, the clock input buffer, and to a second delay segment.

A memory device comprising:

• an address interface;
• a data interface;
• a control interface;
• and
• a SMD clock recovery and skew adjustment circuit comprising,
• a clock input buffer coupled to receive a clock signal,
• a first delay segment coupled to the clock input buffer,
• a forward delay line coupled to the first delay segment,
• an SMD control circuit coupled to the forward delay line and to the clock input buffer, and
• a backward delay line coupled to the SMD control circuit, the clock input buffer, and to a second delay segment.

A DDR memory device interface circuit comprising:

• a data interface;
• a DQS signal interface;
• a data latch coupled to the data interface;
• and
• an SMD clock recovery and skew adjustment circuit coupled to the data latch and coupled to the DQS signal interface, wherein the SMD clock recovery and skew adjustment circuit comprises,
• a clock input buffer coupled to receive a clock signal with a time period,
• a first delay segment coupled to the clock input buffer,
• a forward delay line coupled to the first delay segment,
• an SMD control circuit coupled to the forward delay line and to the clock input buffer, and
• a backward delay line coupled to the SMD control circuit, the clock input buffer, and to a second delay segment.

A method of synchronizing with a clock source comprising:

• coupling a first delay segment to a clock source;
• coupling a forward delay line to the first delay segment;
• coupling an SMD control circuit to the forward delay line and to the clock source;
• and
• coupling a backward delay line to the SMD control circuit and to a second delay segment.

A method of synchronizing a memory device with a clock source comprising:

• receiving a first clock signal on an interface of the memory device;
• coupling the first clock signal from the interface through a first delay segment;
• coupling the first clock signal from the first delay segment through a forward delay line;
• measuring the progress of the first clock signal in the forward delay line with an SMD control circuit upon receiving a second clock signal on the interface;
• inputting the second clock signal and an output of the SMD control circuit to a backward delay line;
• and
• coupling the second clock signal from the backward delay line to a second delay segment.

A method of synchronizing a memory device with a clock signal comprising:

• receiving a first clock signal on an interface of the memory device;
• coupling the first clock signal from the interface through a first delay segment;
• coupling the first clock signal from the first delay segment through a data path model,
• coupling the first clock signal from the data path model through a forward delay line;
• measuring the progress of the first clock signal in the forward delay line with an SMD control circuit upon receiving a second clock signal on the interface;
• coupling the second clock signal from the interface through a first delay segment;
• and
• coupling the second clock signal from the first delay segment and an output of the SMD control circuit to a backward delay line.