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AssigneeSTMicroelectronics S.r.l.
InventorHelene Esch
Estimating the term…
The data storage device includes several registers that can be addressed by address words, and connected to p output ports through connections that can be configured in response to address words of p registers selected to read the contents of these registers on the p ports respectively. All register address words contain a specific bit with a predetermined rank identical for all address words and remaining bits. The registers are connected in pairs on each output port, each pair of registers containing two registers with address words that only differ in the value of the said specific bit. The connections include a pair of first switches that can be controlled in a complementary manner by the specific bit in the address word of one of the two registers, and a second switch connected to the output port considered and that can be controlled from the remaining bits of the address words of the two registers, for each pair of registers and for each output port, the first two switches are connected firstly between the corresponding two registers, and secondly between the corresponding second switch.
Data storage device comprising several registers that can be addressed by address words, and connected to p output ports through connecting means that can be configured in response to address words of p registers selected to read the contents of these registers on the p ports respectively, characterized in that all register address words (MAD) contain a specific bit with a predetermined rank (A) identical for all address words and remaining bits (b0, b1, b2), the registers are connected in pairs on each output port, each pair of registers containing two registers with address words that only differ in the value of the said specific bit, and by the fact that for each pair of registers and for each output port, the connecting means comprise a pair of first switching means (0ITA0.0, 0ITA8.0) that can be controlled in a complementary manner by the specific bit in the address word of one of the two registers, and a second switching means (0ITB0.0) connected to the output port considered (PL0.0) and that can be controlled from the remaining bits of the address words of the two registers, the first two switching means being connected firstly between the corresponding two registers (R0.0, R8.0), and secondly between the corresponding second switching means (0TTB0.0).
Device according to either of the previous claims, characterized by the fact that the first switching means associated with the two registers in a pair are located close to each other.
Device according to either of the previous claims, characterized by the fact that it is made in the form of an integrated circuit.
Device according to either of the previous claims, characterized by the fact that it is controlled by a signal processing processor, in read.
Dependencies are inferred from the claim text.