Top/bottom symmetrical protection scheme for flash
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Kevin C. Widmer
Life of this patent
Estimating the term…
Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of memory cells having N addressable sectors, and control circuitry to control erase or write operations on the array of memory cells. Protection circuitry can be coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors. The protection circuitry can comprise a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector.
Claims9
A method for writing data to a boot area of a synchronous memory device, the method comprising:
- initiating a write operation to the boot area;
- reading data from a register circuit;
- and
- authorizing the write operation to the boot area if the data is in a first state.
A memory device comprising:
- an array of memory cells comprising at least one boot area;
- a data register that stores protect status bits corresponding to a protect status of each boot area;
- and
- a state machine capable of executing a method of writing to each boot area including initiating a write operation to the at least one boot area, reading the protect status bits from the data register, and authorizing the write operation to the at least one boot area if the protect status bits are in a first state.
A memory device comprising:
- an array of memory cells having at least one boot area;
- a non-volatile data register that stores protect status bits indicating a protect status of the at least one boot area;
- a volatile data register corresponding to the non-volatile data register such that the protect status bits are transferred from the non-volatile data register to the volatile data-register;
- and
- control circuitry coupled to the non-volatile and volatile registers to selectively prevent erase or write operations from being performed on the at least one boot area in response to a state of the protect status bits.
A method for writing data to a boot area of a memory device, the method comprising:
- transferring a protect status bit from a non-volatile data register to a volatile data register;
- initiating a write operation to the boot area;
- reading the protect status bit from the volatile data register;
- and
- authorizing the write operation to the boot area if the protect status bit is in a first state.
Dependencies are inferred from the claim text.