System for symmetric pulse generator flip-flop
AssigneeFujitsu Limited
InventorsVolin G. Oklobdzija, William W. Walker, Nikola M. Nedovic
Life of this patent
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Abstract
A Symmetric Pulse Generator Flip-Flop (SPG-FF). The flip-flop comprises two pulse generator stages that each respond to one particular transition of an input clock signal. Thus, the flip-flop is triggered on both the rising and falling edge of the clock signal to capture an input data signal. The outputs of the generator stages are combined to form a flip-flop output.
Claims2
A symmetric pulse generator (SPG) flip-flop that operates to receive an input data signal and an input clock signal to produce a flip-flop output signal, the SPG flip-flop comprising:
- clock logic that receives the input clock signal and produces first, second, and third timing signals;
- a first pulse generator stage that receives the input data signal, the input clock signal, and the first timing signal, and generates a first generator output signal;
- a second pulse generator stage that receives the input data signal, and the second and third timing signals, and generates a second generator output signal;
- and
- logic to combine the first and second generator output signals to produce the flip-flop output signal.
A method for providing a SPG flip-flop that operates to receive an input data signal and an input clock signal to produce a flip-flop output signal, the method comprising steps of:
- producing first, second, and third timing signals from the input clock signal;
- generating a first generator output signal from the input data signal, the input clock signal, and the first timing signal;
- generating a second generator output signal from the input data signal, and the second and third timing signals;
- and
- combining the first and second generator output signals to produce the flip-flop output signal.
Dependencies are inferred from the claim text.