Semiconductor storage device

A semiconductor storage device comprising:

• an array region including a plurality of memory cell array blocks, in each of which a plurality of memory cells are arrayed, the array region being connected to a (k:
• k is a natural number)-number of data input/output lines;
• a (k+m:
• m is a natural number)-number of common internal data lines provided in common to the plurality of memory cell array blocks;
• a (k+m)-number of individual internal data lines provided to each of the plurality of memory cell array blocks;
• an individual line connection circuit for data line redundancy configured to respectively connect a (k to k+m)-number of the (k+m)-number of individual internal data lines to a (k to k+m)-number of the (k+m)-number of common internal data lines, in accordance with a first defect information signal;
• and
• a common line connection circuit for data line redundancy configured to respectively connect a k-number of the (k to k+m)-number of common internal data lines to the k-number of data input/output lines, in accordance with a second defect information signal.

A semiconductor storage device comprising:

• an array region including a plurality of memory cell array blocks, in each of which a plurality of memory cells are arrayed, the array region being connected to a (k:
• k is a natural number)-number of data input/output lines;
• a (k+m:
• m is a natural number)-number of common internal data lines provided in common to the plurality of memory cell array blocks;
• a (k+n:
• n is a natural number)-number of individual internal data lines provided to each of the plurality of memory cell array blocks;
• a k-number of intermediate connection lines provided between the common internal data lines and the individual internal data lines, to each of the plurality of memory cell array blocks;
• an individual line connection circuit for data line redundancy configured to respectively connect a k-number of the (k+n)-number of individual internal data lines to the k-number of intermediate connection lines, in accordance with a first defect information signal;
• a first common line connection circuit for data line redundancy configured to respectively connect a k-number of the (k+m)-number of common internal data lines to the k-number of data input/output lines, in accordance with a second defect information signal;
• and
• a second common line connection circuit for data line redundancy configured to respectively connect the k-number of common internal data lines to the k-number of intermediate connection lines, in accordance with the second defect information signal.