Test circuit of an integrated memory circuit for coding assessment data and method for testing the memory circuit
OwnerDirk Fuhrmann, Peter Beerinventors
Life of this patent
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Abstract
An integrated memory circuit has a memory cell array and a test circuit. The test circuit generates an assessment datum, the assessment datum is dependent on a result of a comparison between a datum read from the memory cell array and a datum previously written to the memory cell array. A coding unit is coupled to the test circuit in order to code a plurality of assessment signals to form a coded test signal, a voltage signal is assigned to the plurality of test data as coded test datum.
Claims11
An integrated memory circuit, comprising:
- a memory cell array;
- a test circuit connected to said memory cell array, said test circuit generating an assessment datum, the assessment datum being dependent on a result of a comparison between a datum read from said memory cell array and a datum previously written to said memory cell array;
- and.
- a coding unit coupled to said test circuit for coding a plurality of assessment data to form a coded test signal, the coded test signal being a voltage signal representing the plurality of assessment data and functioning as a coded test datum.
A tester unit for receiving coded assessment data, comprising:
- a decoding circuit for receiving a coded test signal containing a voltage signal which can assume a plurality of signal levels, said decoding circuit generating a respective pattern of assessment data in response to a voltage level of the voltage signal received.
A test system, comprising:
- an integrated memory circuit, containing:
- a memory cell array;
- a test circuit connected to said memory cell array, said test circuit generating an assessment datum, the assessment datum being dependent on a result of a comparison between a datum read from said memory cell array and a datum previously written to said memory cell array;
- and
- a coding unit coupled to said test circuit for coding a plurality of assessment data to form a coded test signal, the coded test signal being a voltage signal representing the plurality of assessment data and functioning as a coded test datum;
- a tester unit connected to said integrated memory circuit so that the coded test datum can be transmitted to said tester unit.
A method for testing an integrated memory circuit having a memory cell array, which comprises the steps of:
- comparing a datum read from the memory cell array with a datum previously written to the memory cell array;
- generating an assessment datum in dependence on a result of the comparing step;
- coding a plurality of assessment data into a coded test datum;
- transmitting the coded test datum to a tester unit;
- and
- decoding the coded test datum back into the plurality of assessment data.
Dependencies are inferred from the claim text.