Topography correction for testing of redundant array elements

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory elements and a plurality of redundant memory elements;
• and
• a data topography correction circuit including:
• a redundant hit circuit for determining if a redundant memory element has been used to replace a defective memory element of the semiconductor memory device;
• and
• a redundant topology correction scrambler circuit for converting data from a data topology of the defective memory element to a data topology of the redundant memory element.

A method for testing a semiconductor memory device, the method comprising the steps of:

• applying a test mode signal to place the semiconductor memory device in a test mode;
• providing an address of a memory array element of the semiconductor memory device to be tested;
• determining if the memory array element has been replaced with a redundant element;
• and
• if the memory array element has been replaced, correcting test data to a data topology of the redundant element.