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US 2004/0057294 A1Published application
Redundancy scheme for a memory array
OwnerRaj Kumar Jaininventor
Life of this patent
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Abstract
An IC with a memory array comprises a redundancy unit. The redundancy unit includes a tag portion, an address portion, and a redundant memory cell portion. A comparator determines whether an address of a read or a write command matches with the address stored in the address portion of the redundancy unit and switches from the normal data path to the memory cell portion of the redundancy unit.
Claims20
An integrated circuit (IC) comprising:
- an array of memory cells arranged in rows and columns;
- an address bus for receiving addressing information;
- a data-in path for receiving data during a write memory access;
- a signal out path coupled to the memory array for outputting data during a read;
- a data-out path coupled to the signal out path;
- and
- a redundancy unit comprising,
- at least one redundancy element having tag, address, and data portions, the tag portion indicates whether the redundancy element has been programmed for redundancy, the address portion contains a defective address if the redundancy element has been programmed for redundancy, and the data portion contains data associated with the defective address,
- a control circuit for generating an active signal indicating that an access is associated with the defective address,
- a read redundancy control circuit coupled to the output signal path and redundancy unit, and
- a write redundancy control unit coupled to the data in path and redundancy unit.
8 more elements
Dependencies are inferred from the claim text.