Control method of non-volatile semiconductor memory cell and non-volatile semiconductor memory device

Control method of a non-volatile semiconductor memory cell an operation cycle of which consists of a bias-application period for applying bias voltage for data-erase or data-write and verification period for making a result verification after termination of the bias-application period, and pluralities of the operation cycles of which are repeated for erase operation and write operation to the non-volatile semiconductor memory cell, the control method comprising steps of:

• first bias adjustment step where, during a first predetermined period that begins with start of either the erase operation or the write operation, the bias voltage becomes deeper by increment of operation unit including at least one operation cycle along with progress of the erase operation or the write operation and duration of the operation unit is controlled to have positive correlation to voltage difference of preceding operation unit and the bias voltage;
• and
• second bias adjustment step where, during a second predetermined period that comes near with end of either the erase operation or the write operation, the bias voltage becomes deeper by increment of operation unit including at least one operation cycle along with progress of the erase operation or the write operation and duration of operation unit is controlled to be short compared with adjustment time taken by the first bias adjustment step.

Control method of a non-volatile semiconductor memory cell an operation cycle of which consists of a bias-application period for applying bias voltage for data-erase or data-write and verification period for making a result verification after termination of the bias-application period, and pluralities of the operation cycles of which are repeated for erase operation and write operation to the non-volatile semiconductor memory cell, the control method comprising steps of:

• first bias adjustment step where, during a first predetermined period that begins with start of either the erase operation or the write operation, the bias voltage becomes deeper by increment of operation unit including at least one operation cycle along with progress of the erase operation or the write operation and duration of the operation unit is controlled to have positive correlation to voltage difference of preceding operation unit and the bias voltage;
• and
• third bias adjustment step where, during a third predetermined period that comes near with end of either the erase operation or the write operation, voltage difference of the bias voltage between operation units including at least one the operation cycles becomes deeper than voltage difference of the bias voltage in the first bias adjustment step.

A non-volatile semiconductor memory device for conducting erase operation or write operation to a non-volatile semiconductor memory cell by repeating an operation cycle of which consists of a bias-application period to apply bias voltage for data-erase or data-write and a verification period to make a result verification after termination of the bias-application period, the non-volatile semiconductor memory device comprising:

• a control parameter setting section for setting a control parameter for the erase operation or the write operation;
• and
• a control section for controlling the erase operation or the write operation in accordance with the control parameter from the control parameter setting section.