Method of controlling an electronic non-volatile memory and associated device

Method according to any one of the preceding claims, characterized in that at least one state setting step is a programming step, wherein:

• the voltage applied to the control gate is negative;
• and
• the voltage applied to the drain is positive.

Method according to any one of the preceding claims, characterized in that at least one state setting step is an erasing step, wherein:

• the voltage applied to the control gate is positive;
• and
• the voltage applied to the drain is negative.

Method according to any one of the preceding claims, characterized in that the voltages applied simultaneously to the control gate and to the drain have a same amplitude.

Method according to any one of the preceding claims, characterized in that:

• the transistor has a substrate (B);
• the method further comprises a step of applying the drain voltage on the substrate, at least during said state setting step of the cell.

Method according to any one of the preceding claims, characterized in that the amplitudes of said applied voltages are less than 10 volts.

Method according to any one of the preceding claims, characterized in that the potential difference between the control gate and the drain is comprised between 12 and 16 volts during the simultaneous application of the voltages.

Method according to any one of the preceding claims, characterized in that:

• the cell further presents a selection transistor (Msel), whose source (S) is connected to the drain (DF) of the floating gate transistor (Mlec);
• a voltage of less than 12 volts is applied to the gate of the selection transistor, optionally during the cell programming or erasing step.

Electronic device:

• comprising at least one EEPROM memory cell (1) and one cell power supply;
• amenable for implementing the method according to any one of the preceding claims.