Nonvolatile memory cell with a floating gate at least partially located in a trench in a semiconductor substrate

An integrated circuit comprising a nonvolatile memory cell, the integrated circuit comprising:

• a semiconductor substrate having a top surface and a first trench formed in the top surface;
• a dielectric on a surface of the first trench;
• a conductive floating gate at least partially located in the first trench;
• wherein the nonvolatile memory cell comprises a first field effect transistor (FET) whose conductivity is at least partially controlled by the floating gate;
• wherein the substrate comprises:
• a first semiconductor region of a first conductivity type adjacent to the first trench and providing a first source/drain region for the first FET;
• a second semiconductor region of a second conductivity type adjacent to the first trench above the first semiconductor region and providing a channel region for the first FET;
• a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the first trench above the second semiconductor region and provides a second source/drain region for the first FET;
• wherein the integrated circuit further comprises a dielectric region having at least a portion extending below the top surface of the substrate between the first trench and a top part of the third semiconductor region, wherein the third semiconductor region has a part located below said portion of the dielectric region and meeting the first trench.

An integrated circuit comprising:

• a semiconductor substrate having a top surface and a trench formed in the top surface;
• a first dielectric on a surface of the trench;
• a conductive floating gate at least partially located in the trench;
• wherein the nonvolatile memory cell comprises a first field effect transistor (FET) comprising said floating gate;
• wherein the substrate comprises:
• a first semiconductor region of a first conductivity type adjacent to the trench and providing a first source/drain region for the first FET;
• a second semiconductor region of a second conductivity type adjacent to the trench above the first semiconductor region and providing a channel region for the first FET;
• a third semiconductor region of the first conductivity type, wherein at least a portion of the third semiconductor region lies adjacent to the trench above the second semiconductor region and provides a second source/drain region for the first FET;
• wherein the first dielectric comprises a first portion and a second portion, the first portion being stronger against leakage than the second portion, wherein at least part of the first semiconductor region is adjacent to the first portion of the first dielectric, and at least part of the second semiconductor region is adjacent to the second portion of the first dielectric.