Motor control apparatus and motor control method

Abstract

Control data is efficiently serially transferred to a drive device for driving a motor without involving the CPU. Data buffers are allocated at specific memory addresses. An address decoder decodes a memory address output to the address bus and applies a write enable signal to the corresponding data buffer to write data to that data buffer by DMA transfer. When data is written to a data buffer, a sequencer circuit compiles control data, based on data in that data buffers, in a shift register, and serially transfers the control data one bit at a time on a serial transfer line synchronized to a clock.

Dependencies are inferred from the claim text.