Method for improving instruction selection efficiency in a DSP/RISC compiler
OwnerShan-Chyun Kuinventor
Life of this patent
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Abstract
A method for improving instruction selection efficiency in a DSP/RISC compiler. Concurrently obtaining optimal performance and space, the method includes the following steps: determining a semantic tree for a basic block; finding all matching combinations for the semantic tree with reference to a set of patterns; determining cycle number and instruction length for all combinations; filtering the instruction length greater than a predetermined instruction length and extra ones having the same cycle number and instruction length according to the determined cycle number and instruction length; and choosing one combination with the smallest cycle number from the remaining combinations and outputting the one combination as the desired object code.
Claims13
A method for improving instruction selection efficiency in a DSP/RISC compiler, comprising the steps of:
- determining a semantic tree for a basic block;
- finding all matching combinations for the semantic tree with reference to a set of patterns;
- determining cycle number and instruction length for all combinations;
- filtering the instruction length greater than a predetermined instruction length and extra ones having the same cycle number and instruction length according to the determined cycle number and instruction length;
- and
- choosing one combination with the smallest cycle number from the remaining combinations and outputting the one combination to be the desired object code.
Dependencies are inferred from the claim text.