System and methods for pre-artwork signal-timing verification of an integrated circuit design

A method for verifying time-varying signal cooperation across an integrated circuit during various stages of a design life cycle, the method comprising the steps of:

• acquiring circuit information, the circuit information comprising a plurality of functional blocks and a plurality of conductors coupling the functional blocks, wherein the functional blocks are modeled by a plurality of signal characteristics associated with the conductors;
• receiving the timing constraints used in designing and the results of a signal analysis for each respective functional block;
• generating a representation of each functional block;
• and
• applying the representation in a static timing analyzer.

A computer-readable medium having a program for verifying signal timing for an integrated circuit, the program comprising:

• logic configured to receive a representation of a functional block;
• logic configured to receive a timing constraint associated with the functional block;
• logic configured to identify each of a plurality of conductors that traverse a border of the functional block;
• logic configured to model the plurality of conductors;
• and
• logic configured to generate a model of the functional block suitable for application in a static timing analysis.

A computer aided circuit design tool, comprising:

• means for acquiring a representation of a plurality of functional blocks designated for inclusion in an integrated circuit;
• means for acquiring an associated time constraint applied during the design of each of the functional blocks;
• and
• means for identifying the projected worst case signal timing for a signal that originates in an originating block that traverses the interface of a functional block of interest.