Predicting useless accesses
OwnerSangwook Kim, Dhananjay Adhikari +1inventors
InventorsSangwook Kim, Dhananjay Adhikari, Zhong-Ning Cai
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Abstract
A predictor of consecutive useless accesses, wherein consecutive useless accesses to a logic unit are counted and a next useless access is predicted to be within a plurality of ranges. Each of the plurality of ranges has a corresponding confidence predictor to track and provide a confidence level of whether a next access to the logic unit will be useless.
Claims43
An apparatus comprising:
- a first unit to perform at least one function within a computer system;
- a second unit to make a prediction of whether an access to the first unit will yield a desired result;
- a third unit to determine a confidence level of the prediction;
- a fourth unit to disable the first unit if the second unit predicts that the access to the first unit will not yield a desired result and the third unit determines that the confidence level of the prediction is equal to or greater than a predetermined value.
A system comprising:
- a cache memory;
- a bus agent to access the cache memory;
- a useless access prediction unit to predict whether an access to the cache memory will yield a desired result, the useless access prediction unit comprising a plurality of comparitors to compare a number of consecutive useless accesses to the cache memory to a plurality of threshold values, the useless access prediction unit further comprising a plurality of state machines to provide a confidence level of whether the number of consecutive useless accesses is between a first and second threshold value.
An apparatus comprising:
- means for counting a number of useless consecutive accesses to at least one of a plurality of parallel logic units;
- means for comparing the number of useless consecutive accesses with a plurality of threshold values;
- means for predicting whether a next access to at least one of the plurality of logic units will be useless;
- means for disabling the at least one of the plurality of logic units if the means for predicting predicts that the next access will be useless.
A method comprising:
- accessing a first cache memory;
- counting a first consecutive number of cache misses to the first cache memory;
- comparing the first consecutive number of cache misses to a first and second threshold value;
- predicting that an access to the first cache memory subsequent to the first consecutive number of cache misses will be a miss if the first consecutive number of cache misses is less than the second threshold value and greater or equal to the first threshold value and a prediction confidence is equal to or greater than a first confidence level.
A machine-readable medium having stored thereon a set of instructions, which when executed by a machine cause the machine to perform a method comprising:
- monitoring an access of a plurality of logic units;
- conserving power in a computer system by predicting a consecutive useless access to at least one logic unit of the plurality of logic units and subsequently disabling the logic unit, the predicting being dependent upon a previous number of useless consecutive accesses to the logic unit, the previous number being greater than or equal to a first threshold value and less than a second threshold value.
Dependencies are inferred from the claim text.