Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache

A method for reducing power in multi-way set associative arrays comprising:

• (a) detecting when a next cache access, immediately following a current cache access, will be taken from a first same cache way that the current cache access takes;
• (b) signaling all cache ways, except said first same cache way, not to access information from their respective arrays when step (a) occurs;
• (c) signaling all tag arrays to not access information from their respective arrays when step (a) occurs;
• (d) disabling power to all compare circuits in said multi-way associative arrays when step (a) occurs.

A method for reducing power in multi-way set associative arrays comprising:

• (a) detecting when a next cache access, immediately following a current cache access, will be taken from a first same cache way that the current cache access takes;
• (b) halting all clocks connected to all cache ways, except said first cache way, when step (a) occurs
• (c) signaling all tag arrays to not access information from their respective arrays when step (a) occurs;
• (d) disabling power to all compare circuits in said multi-way associative arrays when step (a) occurs.

A method for reducing power in multi-way set associative arrays comprising:

• (a) detecting when a next cache access, immediately following a current cache access, will be taken from a first same cache way that the current cache access takes;
• (b) not charging all bit-lines in all cache ways, except said first cache way, when step (a) occurs
• (c) signaling all tag arrays to not access information from their respective arrays when step (a) occurs;
• (d) disabling power to all compare circuits in said multi-way associative arrays when step (a) occurs.

A method for reducing power in multi-way set associative arrays comprising:

• (a) detecting when a next cache access, immediately following a current cache access, will be taken from a first same cache way that the current cache access takes;
• (b) disabling power to all sense amps in all cache ways, except said first cache way, when step (a) occurs
• (c) signaling all tag arrays to not access information from their respective arrays when step (a) occurs;
• (d) disabling power to all compare circuits in said multi-way associative arrays when step (a) occurs.

A method for reducing power in multi-way set associative arrays comprising:

• (a) detecting when a next cache access, immediately following a current cache access, will be taken from a first same cache way that the current cache access takes;
• (b) signaling all cache ways, except said first same cache way, not to access information from their respective arrays when step (a) occurs;
• (c) halting all clocks connected to all tag arrays when step (a) occurs
• (d) disabling power to all compare circuits in said multi-way associative arrays when step (a) occurs.

A method for reducing power in multi-way set associative arrays comprising:

• (a) detecting when a next cache access, immediately following a current cache access, will be taken from a first same cache way that the current cache access takes;
• (b) signaling all cache ways, except said first same cache way, not to access information from their respective arrays when step (a) occurs;
• (c) not charging all bit lines connected to all tag arrays when step (a) occurs;
• (d) disabling power to all compare circuits in said multi-way associative arrays when step (a) occurs.

A method for reducing power in multi-way set associative arrays comprising:

• (a) detecting when a next cache access, immediately following a current cache access, will be taken from a first same cache way that the current cache access takes;
• (b) signaling all cache ways, except said first same cache way, not to access information from their respective arrays when step (a) occurs;
• (c) disabling power to all sense amps in all tag arrays when step (a) occurs
• (d) disabling power to all compare circuits in said multi-way associative arrays when step (a) occurs.

A method for reducing power in multi-way set associative arrays comprising:

• (a) detecting when a next cache access is used to gather addition information for a current cache line;
• (b) signaling all cache ways, except said first same cache way, not to access information from their respective arrays when step (a) occurs;
• (c) signaling all tag arrays to not access information from their respective arrays when step (a) occurs;
• (d) disabling power to all compare circuits in said multi-way associative arrays when step (a) occurs.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a logic circuit that detects when a next cache access will occur in a same cache way as a current cache access;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said logic circuit signals all said cache ways, except said same cache way, to not access information from all said cache ways except said same cache way;
• (f) wherein said logic circuit signals all said tag arrays to not access information from said tag arrays;
• (g) wherein said logic circuit disables power to all said compare circuits.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a logic circuit that detects when a next cache access will occur in a same cache way as a current cache access;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said logic circuit signals all said cache ways, except said same cache way, to halt all clocks contained in all said cache ways except said same cache way;
• (f) wherein said logic circuit signals all said tag arrays to not access information from said tag arrays;
• (g) wherein said logic circuit disables power to all said compare circuits.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a logic circuit that detects when a next cache access will occur in a same cache way as a current cache access;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said logic circuit signals all said cache ways, except said same cache way, to not charge all bitlines in said cache ways except said same cache way;
• (f) wherein said logic circuit signals all said tag arrays to not access information from said tag arrays;
• (g) wherein said logic circuit disables power to all said compare circuits.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a logic circuit that detects when a next cache access will occur in a same cache way as a current cache access;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said logic circuit signals all said cache ways, except said same cache way, to disable power to all sense amps in all said cache ways except said same cache way;
• (f) wherein said logic circuit signals all said tag arrays to not access information from said tag arrays;
• (g) wherein said logic circuit disables power to all said compare circuits.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a logic circuit that detects when a next cache access will occur in a same cache way as a current cache access;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said logic circuit signals all said cache ways, except said same cache way, to not access information from all said cache ways except said same cache way;
• (f) wherein said logic circuit signals all said tag arrays to halt all clocks in said tag arrays;
• (g) wherein said logic circuit disables power to all said compare circuits.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a logic circuit that detects when a next cache access will occur in a same cache way as a current cache access;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said logic circuit signals all said cache ways, except said same cache way, to not access information from all said cache ways except said same cache way;
• (f) wherein said logic circuit signals all said tag arrays to not charge all bitlines in said tag arrays;
• (g) wherein said logic circuit disables power to all said compare circuits.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a logic circuit that detects when a next cache access will occur in a same cache way as a current cache access;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said logic circuit signals all said cache ways, except said same cache way, to not access information from all said cache ways except said same cache way;
• (f) wherein said logic circuit signals all said tag arrays to disable power to all sense amps in said tag arrays;
• (g) wherein said logic circuit disables power to all said compare circuits.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a means for detecting when a next cache access will occur in a same cache way as a current cache access;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said detecting means signals all said cache ways, except said same cache way, to not access information from all said cache ways except said same cache way;
• (f) wherein said detecting means signals all said tag arrays to not access information from said tag arrays;
• (g) wherein said detecting means disables power to all said compare circuits.

A circuit for reducing power in multi-way set associative arrays comprising:

• (a) a means for detecting when a next cache access is used to gather additional information for a current cache line;
• (b) a plurality of cache ways;
• (c) a plurality of tag arrays;
• (d) a plurality of compare circuits;
• (e) wherein said detecting means signals all said cache ways, except said same cache way, to not access information from all said cache ways except said same cache way;
• (f) wherein said detecting means signals all said tag arrays to not access information from said tag arrays;
• (g) wherein said detecting means disables power to all said compare circuits.