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US 2004/0024967 A1Published application
Reducing tag-ram accesses and accelerating cache operation during cache miss
AssigneeTexas Instruments Incorporated
InventorJonathan Y. Zhang
Life of this patent
Estimating the term…
Abstract
This invention is a cache memory employing a tag bypass controller to detect a memory access to the same cache line as a last cache miss address and a last cache hit address. This information is uses for efficient data accesses and forwarding. Registers store the last miss-address and the last hit-address and corresponding valid flags. These hardware features allow reduced tag-RAM accesses and greatly reduce the latency required to fully re-stock a missed cache line.
Claims6
A method modifying cache operation comprising the steps of:
- storing a last cache-miss address;
- storing a last cache-hit address;
- on each memory access, comparing a fetch memory address with both the last cache-miss address and the last cache-hit address;
- if a match occurs bypassing access to a tag-RAM and requesting data from a cache data-RAM;
- and
- if a non-match occurs, accessing the tag-RAM to determine if data is stored in the cache data-RAM.
3 more elements
An apparatus performing cache memory control comprised of:
- a last miss-address register storing a last cache miss address of a last memory access request address which generated a cache miss;
- a last hit-address register a last cache hit address of a last memory access request address which generated a cache hit;
- a cache line comparator comparing a current memory access request address to both said last miss-line address and said last hit-line address and providing a match indication or a non-match indication;
- a cache data-RAM storing data and corresponding memory addresses;
- a tag-RAM storing indications of addresses of data stored in cache data-RAM;
- a tag-RAM controller connected to said cache line comparator and said tag-RAM, said tag-RAM controller operative to
- prohibit access to said tag-RAM to determine if data corresponding to said current memory access request address is stored in said cache data-RAM if said cache line comparator provides said match indication, and
- enable access to said tag-RAM to determine if data corresponding to said current memory access request address is stored in said cache data RAM if said cache line comparator provides said non-match indication.
5 more elements
Dependencies are inferred from the claim text.