CAM diamond cascade architecture

A system of content addressable memories arranged in logical levels for receiving a clock signal, each logical level of content addressable memories receiving a search instruction in successive clock cycles and each content addressable memory generating local match data in response to the search instruction, the system comprising:

• a first content addressable memory in a first logical level for providing first match data corresponding to its local match data in a first clock cycle;
• a second content addressable memory in a second logical level for receiving the first match data, and for providing second match data corresponding to the highest priority match data between its local match data and the first match data in a second clock cycle;
• a third content addressable memory in the second logical level for receiving the first match data, and for providing third match data corresponding to the highest priority match data between its local match data and the first match data in the second clock cycle;
• a fourth content addressable memory in a third logical level for receiving the second match data, and for providing fourth match data corresponding to the highest priority match data between its local match data and the second match data in a third clock cycle;
• a fifth content addressable memory in the third logical level for receiving the second match data, and for providing fifth match data corresponding to the highest priority match data between its local match data and the second match data in the third clock cycle;
• a sixth content addressable memory in the third logical level for receiving the third match data, and for providing sixth match data corresponding to the highest priority match data between its local match data and the third match data in the third clock cycle;
• a seventh content addressable memory in the third logical level for receiving the third match data, and for providing seventh match data corresponding to the highest priority match data between its local match data and the third match data in the third clock cycle;
• an eighth content addressable memory in a fourth logical level for receiving the fourth and fifth match data, and for providing eighth match data corresponding to the highest priority match data between its local match data, the fourth match data and the fifth match data in a fourth clock cycle;
• a ninth content addressable memory in the fourth logical level for receiving the sixth and seventh match data, and for providing ninth match data corresponding to the highest priority match data between its local match data, the sixth match data and the seventh match data in the fourth clock cycle;
• and, a tenth content addressable memory in a fifth logical level for receiving the eighth and ninth match data, and for providing final match data corresponding to the highest priority match data between its local match data, the eighth match data and the ninth match data in a fifth clock cycle.

A method of searching a system of content addressable memories for a match address after passing a search instruction to each content addressable memory, comprising:

• a) generating input match address data in an input content addressable memory in response to the search instruction;
• b) comparing in parallel the input match address data and respective local match address data generated from parallel content addressable memory networks to determine intermediate match address data corresponding to each parallel content addressable memory network;
• and,
• c) comparing the intermediate match address data and output match address data generated in an output content addressable memory to determine a system match address.