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US 2004/0024952 A1Published application
Techniques to map cache data to memory arrays
AssigneeIntel Corporation
InventorsKuljit S. Bains, Herbert Hum, John Halbert
Life of this patent
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Abstract
Methods and apparatuses for mapping cache contents to memory arrays. In one embodiment, an apparatus includes a processor portion and a cache controller that maps the cache ways to memory banks. In one embodiment, each bank includes data from one cache way. In another embodiment, each bank includes data from each way. In another embodiment, memory array banks contain data corresponding to sequential cache lines.
Claims30
An apparatus comprising:
- a processor portion;
- a cache controller coupled to the processor portion, said cache controller to map each of a plurality of cache ways to each bank of a plurality of banks of a memory array.
An apparatus comprising:
- a processor portion;
- a cache controller coupled to the processor portion and configured to map each bank of a memory array to one cache way.
A method comprising:
- performing a tag lookup to determine if an address is cached in a multi-way associative cache memory;
- selecting one of a plurality of memory banks based on which way provides a hit.
A method comprising:
- performing a tag lookup to determine if an address is cached in an N-way associative cache memory;
- selecting one of N ways from a bank based on the tag lookup.
An apparatus comprising:
- a processor portion;
- a cache controller to generate an address in response to a request from the processor portion, said cache controller to map sequential cache lines to different memory banks;
- a first multi-bank memory to output data corresponding to a first cache line from a first bank in response to the address, wherein a next sequential cache line which is sequential in address to said first cache line is mapped to a different bank.
A system comprising:
- a main memory;
- a memory controller coupled to the main memory;
- a processor coupled to the memory controller, the processor comprising:
- first level cache;
- an N-way associative cache comprising:
- a cache controller, said cache controller to map cache ways to particular memory banks;
- a plurality of multi-bank memory arrays simultaneously accessible by the cache controller to assemble a cache line.
4 more elements
Dependencies are inferred from the claim text.