Programmable controller
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKotaro Fujiwara, Yuuichi Tachi, Kazuaki Miyabe, Tamiki Kobayashi
Life of this patent
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKotaro Fujiwara, Yuuichi Tachi, Kazuaki Miyabe, Tamiki Kobayashi
Estimating the term…
When a decoding circuit (22a) decodes an instruction code stored in a pipeline register (21d), the decoding circuit (22a) decodes the device address. Based on this, it is decided which one of the device information of a RAM (11) and a RAM (12) is to be used. When the area of the RAM (12) has been assigned, the decoding circuit (22a) outputs a signal showing that the number of stop of pipeline processing is 0, unlike the assignment of the RAM (11). Therefore, a pipeline register section (21) does not set the pipeline stop signal to 1. Consequently, the reading of the instruction code from the RAM (11) and the pipeline processing are not interrupted. As a result, it is possible to realize a structure in which execution of a high-speed processing is possible and a compact/low-cost structure in the same hardware.
A programmable controller that carries out a pipeline processing of sequence programs, comprising:
Dependencies are inferred from the claim text.